Reply To: Vhdl test bench U Output
Why OSVVM™? › Forums › VHDL › Vhdl test bench U Output › Reply To: Vhdl test bench U Output
Jim LewisI don’t see anything on OSVVM in your question, so it is probably better to ask these sort of things on Stack Overflow.
I don’t see anything obvious wrong with your testbench. Are the inputs getting to the design correctly? If they are then it is a matter of debugging your design – not your testbench.
To debug your design, use the simulator to view waveforms that are internal to your design. Use breakpoints to look at how a process runs. Breakpoints are easy. Bring up the code you are interested in looking at in your simulator. Select on the left side of a line to set a break point – a large dot should appear before the line. Some lines are not executable, so you cannot set a breakpoint there.