I have a question regarding signal access.
Can we access signals from the test harness in the test?
The signals I want to access are dut signals. Or do we need to access it from the test control?
Basically, I just want to read the signal value of the DUT upon reset.
I try to user either a Verification Component or a Monitor to provide an abstraction layer for all interactions with the DUT.
If there need to be exceptions to this, then you can use external names in TestCtrl to access items from the DUT. To make this feasible, when creating the test harness (top level netlist that connects DUT, VC, and TestCtrl) make sure to instance the DUT first and TestCtrl last.
To use external names, the language a referenced item must already be elaborated. VHDL elaboration of the test harness is top to bottom. The order of instances in the test harness then allows TestCtrl to access signals in the test harness, the DUT or any VC.