Coverage and sequences

[Ledoux]

*Hello

I’m doing a testbench for an ALU.

In SystemVerilog is possible to create a bin for a sequence of ALU operations for example:

 typedef enum {add, sub, mult, and, or, xor, nand, nor} op_t;

op_t AluOp;

  ent1: coverpoint AluOp
     {

         bins l1  = (and => or => mult);

         bins l2  = (mult => mult => add);

     }

This bin will be activated only if those operation happen in this sequence. Is it possible to write a bin like that with OSVVM?

[Jim Lewis]

Sure, it is easy.   Sequences imply history.   We create history explicitly just like RTL – by using clocked processes / flip-flops.  

Once you have history, this is just a simple cross product of selected current values and two previous values.  

WRT sampling, in OSVVM, we trigger on transaction completion using an explicit call to ICover.

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