Does VHDL contain functions like Verilog $readmemb and $readmemh?

[Hassan]

Verilog/SystemVerilog (synthesis) has some functions that can read a file into a signal. These are $readmemb and $readmemh. These can both be used to easily create a ROM from file contents. As far as I know, VHDL does not contain anything along these lines that will work in synthesis. Is this true? If so, why is this so?

[Jim Lewis]

Hi Hassan,
For the OSVVM MemoryPkg, see FileReadH and FileReadB as well as their counter parts FileWriteH and FileWriteB.

For simulation based RAMS, you want to be using OSVVM’s MemoryPkg as it creates sparse memory data structures – ie it only allocates blocks of memory (in 1 K chunks) if you write to a particular location.

Best Regards,
Jim

[Hassan]

Thanks.

My question is actually about synthesizeable code rather than simulation and thus I have put it under VHDL rather than OSVVM.

[Author]

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