FIFO example improvements

[Jon Skull]

Just a minor suggestion to improve the FIFO example – the testbench really ought to check the correctness of the read data.

I understand that this is not the main focus of the example, but someone might unwittingly use the testbench without realising that it is not complete.

Also this would be a good way to start to address the thorny issue of how to write golden reference models in VHDL testbenches (for the FIFO tb you might want a nice untimed queue with a procedural interface and unlimted storage!) – I would love to see some OS-VVM ‘standardisation’ activity on golden reference models.

[Srinivasan Venkataramanan]

* I also noticed that the FIFO example uses:

<code>

use work.RandomBasePkg.all ; 

</code>
I believe something like this is far better approach:

<code>

library osvvm;

use osvvm.RandomBasePkg.all ; 

</code>
Questa 10.2 actually ships OSVVM precompiled and the above change makes it work out of the box (no need to recompile the OSVVM sources, though one could say we use -incr flow). 
Any comments?
Also - has anyone tried this on IUS 12.2 release from Cadence? That's our next step at CVC, will update here on our findings soon.
If we do agree the above fix is useful, how do we submit the changes/contributions to the examples?
RegardsSriniwww.cvcblr.com/blog 

[Daniel Leu]

I second the opinion to use a dedicated library OSVVM instead of work.

[Ian Gibbins]

Regarding the example : the code can be updated easily, the documentation requires careful update with it. It is on schedule right now.

I have also received good news – precompiled OS-VVM will be included in the nearest releases of Aldec tools.

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