GENERATION OF RANDOM BYTES USING RANDOM PACKAGE ONLY

[Nagella]

HI,

I am trying to generate a random bytes to the uart transmitter module.But in the output waveform only one byte is generated throughout the simulation…below is a piece of testbench code if anything is wrong pls correct me.
note:uat_data is a input signal to the uart transmitter module.
process
variable RV:RandomPType;
variable b:std_logic_vector( 7downto 0);
begin
RV.Initseed(RV’instance_name);
wait until reset=’1′ and rising_edge(clk);
b:=RV.RandSlv(0,255,8);
uat_data<=b;
end process;

[Jim Lewis]

Hi Nagella
To debug your code start by reading your code out loud. Do at least 2 iterations of your process.

What we see is that you are calling InitSeed before generating each data value.

Why is this a problem? Verification uses pseudo random. Each seed always produces the same sequence of values. For verification pseudo random is required so your tests are repeatable or stable. When you fix a bug, you need the same sequencing (test case) that caused the failure to run to verify the fix.

You need a loop so your InitSeed only runs once.

If you want to infinitely generate data use something like the following:

process
  variable RV:RandomPType;
  variable b:std_logic_vector( 7downto 0);
begin
  RV.Initseed(RV’instance_name);
  loop
    wait until reset=’1? and rising_edge(clk);
    b:=RV.RandSlv(0,255,8);
    uat_data<=b;
  end loop ;
end process;

Jim

[Nagella]

Hi Lewis,

the above provided code with loop statement gives simulator busy message in console box.

[Jim Lewis]

Hi Nagella,
I typically use an active low reset (ie: 0 when active). Did I guess wrong in your case?
Let me be a little more abstract. Lets assume the constant ACTIVE has the value that
reset has when it is active.

process
  variable RV:RandomPType;
  variable b:std_logic_vector( 7 downto 0);
begin
  RV.Initseed(RV’instance_name);
  -- if reset not started, wait until it starts
  if reset /= ACTIVE then
    wait until reset = ACTIVE ;
  end if ; 
  -- wait until reset cycle is done
  wait until reset /= ACTIVE ;
  loop
    wait until rising_edge(clk);
    b:=RV.RandSlv(0,255,8);
    uat_data<=b;
  end loop ;
end process;

Best Regards,
Jim

[Author]

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