Yep, you touched it! And for a reason that is completely, absolutely unnecessary. The advised code (qualified expression) works on all tools, so there is no reason to use a pre-processor/compiler directive.
Such crutches are often needed in poorly specified languages like Verilog/SV, because of misunderstandings about what the correct compiler/language behavior actually should be, due to the lack of a complete, formal specification for the language.
Furthermore, once allowed, these hacks work their way into standard libraries and usage models (UVM!), instead of fixing the shortcomings of the language and/or SV library itself.