Running example test-benches with GHDL
July 19, 2021 at 13:22 #1832IztokMember
I tried to run the latest Git version of OSVVM with the latest Git version of GHDL, all on Ubuntu 20.04.
Two tests I tried (AXI4Lite, UART) failed with what seems to be GHDL failures rather early into the build process (before simulation). Am I doing something wrong? Is this a known issue? Is there a combination of GHDL/OSVVM release tags, which should be working properly?
$ export PATH=/opt/ghdl/git-mcode/bin:$PATH $ mkdir sim $ cd sim $ rlwrap tclsh % source ../Scripts/StartUp.tcl GHDL-2.0.0-dev % build ../OsvvmLibraries.pro creating directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev creating directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/results library default creating library directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/default/v08 Build Start time 14:15:18 creating directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/logs/GHDL-2.0.0-dev Transcript /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/logs/GHDL-2.0.0-dev/verification_OsvvmLibraries.log set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries source /home/ijeras/Cosylab/verification/OsvvmLibraries/OsvvmLibraries.pro set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/osvvm source /home/ijeras/Cosylab/verification/OsvvmLibraries/osvvm/osvvm.pro library osvvm creating library directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/osvvm/v08 analyze ResolutionPkg.vhd analyze NamePkg.vhd analyze NameStorePkg.vhd analyze OsvvmGlobalPkg.vhd analyze VendorCovApiPkg.vhd analyze TranscriptPkg.vhd analyze TextUtilPkg.vhd analyze AlertLogPkg.vhd analyze MessagePkg.vhd analyze SortListPkg_int.vhd analyze RandomBasePkg.vhd analyze RandomPkg.vhd analyze RandomProcedurePkg.vhd analyze CoveragePkg.vhd analyze MemoryPkg.vhd analyze ScoreboardGenericPkg.vhd analyze ScoreboardPkg_slv.vhd analyze ScoreboardPkg_int.vhd analyze ResizePkg.vhd analyze TbUtilPkg.vhd analyze OsvvmContext.vhd set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/Common source /home/ijeras/Cosylab/verification/OsvvmLibraries/Common/Common.pro library OSVVM_Common creating library directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/osvvm_common/v08 analyze ./src/StreamTransactionPkg.vhd analyze ./src/AddressBusTransactionPkg.vhd analyze ./src/AddressBusResponderTransactionPkg.vhd analyze ./src/AddressBusVersionCompatibilityPkg.vhd analyze ./src/ModelParametersPkg.vhd analyze ./src/FifoFillPkg_slv.vhd analyze ./src/InterruptHandler.vhd analyze ./src/InterruptHandlerComponentPkg.vhd analyze ./src/OsvvmCommonContext.vhd set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/UART source /home/ijeras/Cosylab/verification/OsvvmLibraries/UART/UART.pro library osvvm_uart creating library directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/osvvm_uart/v08 analyze ./src/UartTbPkg.vhd analyze ./src/ScoreboardPkg_Uart.vhd analyze ./src/UartTxComponentPkg.vhd analyze ./src/UartRxComponentPkg.vhd analyze ./src/UartContext.vhd analyze ./src/UartTx.vhd analyze ./src/UartRx.vhd set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4 source /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/AXI4.pro set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/common source /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/common/common.pro library osvvm_axi4 creating library directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/osvvm_axi4/v08 analyze ./src/Axi4LiteInterfacePkg.vhd analyze ./src/Axi4InterfacePkg.vhd analyze ./src/Axi4CommonPkg.vhd analyze ./src/Axi4ModelPkg.vhd analyze ./src/Axi4OptionsPkg.vhd analyze ./src/Axi4VersionCompatibilityPkg.vhd set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/Axi4Lite source /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/Axi4Lite/Axi4Lite.pro library osvvm_axi4 analyze ./src/Axi4LiteMasterComponentPkg.vhd analyze ./src/Axi4LiteResponderComponentPkg.vhd analyze ./src/Axi4LiteMemoryComponentPkg.vhd analyze ./src/Axi4LiteMonitorComponentPkg.vhd analyze ./src/Axi4LiteContext.vhd analyze ./src/Axi4LiteMaster.vhd analyze ./src/Axi4LiteMonitor_dummy.vhd analyze ./src/Axi4LiteResponder_Transactor.vhd analyze ./src/Axi4LiteMemory.vhd set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/AxiStream source /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/AxiStream/AxiStream.pro library osvvm_axi4 analyze ./src/AxiStreamOptionsPkg.vhd analyze ./src/AxiStreamTbPkg.vhd analyze ./src/AxiStreamTransmitter.vhd analyze ./src/AxiStreamTransmitterVti.vhd analyze ./src/AxiStreamReceiver.vhd analyze ./src/AxiStreamReceiverVti.vhd analyze ./src/AxiStreamComponentPkg.vhd analyze ./src/AxiStreamContext.vhd analyze ./src/AxiStreamGenericSignalsPkg.vhd analyze ./src/AxiStreamSignalsPkg_32.vhd set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/Axi4 source /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/Axi4/Axi4.pro library osvvm_axi4 analyze ./src/Axi4ComponentPkg.vhd analyze ./src/Axi4ComponentVtiPkg.vhd analyze ./src/Axi4Context.vhd analyze ./src/Axi4Master.vhd analyze ./src/Axi4MasterVti.vhd analyze ./src/Axi4Monitor_dummy.vhd analyze ./src/Axi4Responder_Transactor.vhd analyze ./src/Axi4ResponderVti_Transactor.vhd analyze ./src/Axi4Memory.vhd analyze ./src/Axi4MemoryVti.vhd Build Start time 14:15:18 CEST Mon Jul 19 2021 Build Finish time 14:15:24, Elasped time: 0:00:06 Stop Transcript /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/logs/GHDL-2.0.0-dev/verification_OsvvmLibraries.log % % % build ../AXI4/Axi4Lite/testbench/ Build Start time 14:15:35 Transcript /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/logs/GHDL-2.0.0-dev/Axi4Lite_testbench.log set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/Axi4Lite/testbench source /home/ijeras/Cosylab/verification/OsvvmLibraries/AXI4/Axi4Lite/testbench/testbench.pro library osvvm_TbAxi4Lite creating library directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/osvvm_tbaxi4lite/v08 analyze TestCtrl_e.vhd analyze TbAxi4.vhd analyze TbAxi4_BasicReadWrite.vhd analyze TbAxi4_ReadWriteAsync1.vhd analyze TbAxi4_ReadWriteAsync2.vhd analyze TbAxi4_ReadWriteAsync3.vhd analyze TbAxi4_RandomReadWrite.vhd analyze TbAxi4_RandomReadWriteByte.vhd analyze TbAxi4_TimeOut.vhd analyze TbAxi4_WriteOptions.vhd simulate TbAxi4_BasicReadWrite Simulate Start time 14:15:36 ghdl --elab-run ended with error ******************** GHDL Bug occurred *************************** Please report this bug on https://github.com/ghdl/ghdl/issues GHDL release: 2.0.0-dev (tarball) [Dunoon edition] Compiled with GNAT Version: 9.3.0 Target: x86_64-linux-gnu /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/ Command line: ghdl --elab-run --std=08 --syn-binding --work=osvvm_TbAxi4Lite --workdir=/home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/osvvm_tbaxi4lite/v08 -P/home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev TbAxi4_BasicReadWrite Exception ORTHO_CODE.SYNTAX_ERROR raised Exception information: raised ORTHO_CODE.SYNTAX_ERROR : ortho_code-exprs.adb:462 Call stack traceback locations: 0x55d152de9a51 0x55d152deb5f6 0x55d152e026fd 0x55d15309d1d8 0x55d1530a02d4 0x55d15308aa28 0x55d15308fe2f 0x55d1530f7e52 0x55d15305f165 0x55d15305c2b8 0x55d15306a3fa 0x55d1530fc4b5 0x55d15303a779 0x55d152f6f5d1 0x55d1530ffdd2 0x55d152d12af7 0x7f77351680b1 0x55d152d111fc 0xfffffffffffffffe ****************************************************************** child process exited abnormally Simulate Finish time 14:15:37, Elasped time: 0:00:01 Build Start time 14:15:35 CEST Mon Jul 19 2021 Build Finish time 14:15:37, Elasped time: 0:00:02 Stop Transcript /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/logs/GHDL-2.0.0-dev/Axi4Lite_testbench.log % % % build ../UART/testbench Ending Previous Simulation Build Start time 14:15:45 Transcript /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/logs/GHDL-2.0.0-dev/UART_testbench.log set CURRENT_WORKING_DIRECTORY /home/ijeras/Cosylab/verification/OsvvmLibraries/UART/testbench source /home/ijeras/Cosylab/verification/OsvvmLibraries/UART/testbench/testbench.pro library osvvm_TbUart creating library directory /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/VHDL_LIBS/GHDL-2.0.0-dev/osvvm_tbuart/v08 analyze TestCtrl_e.vhd analyze TbUart.vhd analyze TbUart_SendGet1.vhd analyze TbUart_SendGet2.vhd analyze TbUart_Options1.vhd analyze TbUart_Options2.vhd analyze TbUart_Checkers1.vhd analyze TbUart_Checkers2.vhd analyze TbUart_Scoreboard1.vhd analyze TbUart_Overload1.vhd simulate TbUart_SendGet1 Simulate Start time 14:15:47 ghdl --elab-run ended with error ghdl:error: overflow detected in process .tbuart(testharness).uartrx_1@uartrx(model).P1 from: process osvvm_uart.uartrx(model).P1 at UartRx.vhd:359 ghdl:error: simulation failed child process exited abnormally Simulate Finish time 14:15:48, Elasped time: 0:00:01 Build Start time 14:15:45 CEST Mon Jul 19 2021 Build Finish time 14:15:48, Elasped time: 0:00:03 Stop Transcript /home/ijeras/Cosylab/verification/OsvvmLibraries/sim/logs/GHDL-2.0.0-dev/UART_testbench.log % % exitJuly 19, 2021 at 15:28 #1833
I am running GHDL version: GHDL 2.0.0-dev (1.0.0.r292.g3807826b) [Dunoon edition]
This is from one of the nightly builds. All of 2021.06 compiles. All of 2021.06 simulates except Axi4Lite – Axi4 Full was updated to work with GHDL – so you can use that instead. The Axi4Lite updates will be coming later this year.July 20, 2021 at 02:01 #1834
This is currently what I am running in the OSVVM libraries for regression:
build ../OsvvmLibraries # Run Tests build ../OsvvmLibraries/UART/RunAllTests.pro build ../OsvvmLibraries/AXI4/AxiStream/RunAllTests.pro build ../OsvvmLibraries/AXI4/Axi4/RunAllTests.pro # Next one has failures in running tests build ../OsvvmLibraries/AXI4/Axi4Lite/RunAllTests.proJuly 20, 2021 at 02:33 #1835
I should also note that the Virtual Transaction Interfaces (VC with suffix of Vti) use external names and GHDL does not support external names.July 20, 2021 at 10:22 #1836IztokMember
I was able to get the Axi4 and Axi4-Stream tests to work.
The above log also list the UART test, which is still failing (I checked again today).
ghdl --elab-run ended with error ghdl:error: overflow detected in process .tbuart(testharness).uartrx_1@uartrx(model).P1 from: process osvvm_uart.uartrx(model).P1 at UartRx.vhd:359 ghdl:error: simulation failed
I was not able to find (in the Scripts repo) an option to enable
.ghwwaveforms with GHDL.
Is there a preferred way to enable waveforms
I noticed you are using AXI4Master and Axi4Responder instead of slave.
The AMBA AXI4 standard document from version H.b on (IHI0022H_c_amba_axi_protocol_spec.pdf) is using new terminology:
Regularized terminology to use Manager to indicate the agent that
initiates transactions and Subordinate to indicate the agent that
receives and responds to requests.July 27, 2021 at 20:00 #1840
Are you running Ubuntu with the GCC build? Try either the mcode or lvvm. Unai setup CI for OSVVM. Prior to this I was testing OSVVM only on Windows 10 with 64 bit llvm. In testing we found that Ubuntu with GCC is not working for some items. I have not looked at the bugs, however, since it works for Ubuntu with mcode and lvvm and widows 10 with 32bit mcode and 64 bit llvm, I suspect it is something that GHDL needs to address.
You can see the CI results at: https://github.com/OSVVM/OsvvmLibraries/actions
The scripts do not currently at save .ghw waveforms. I would accept a pull request for this on GitHub if you know the options that are needed with the scripts.
Thanks for the update on AXI terminology. I had updated ours before they updated theirs. In fact, I submitted a bug against their documentation requesting a change.
I will get the names updated shortly to match theirs – although they picked poorly. I looked for names that were used naturally in the description, hence, I would have come up with initiator (nice as it matches PCI) and responder (matching what we initially picked for OSVVM). They got stuck in the same conundrum we did when a group of Open Source people talked about the naming – we were looking for synonyms of the current terminology – this results in names that do not come naturally – oh well.August 4, 2021 at 20:20 #1843
Apparently the mcode version of GHDL errors out if you subtract 1 from an uninitialized integer.
All other simulators are ok with this. OTOH, it was easy enough to fix. So there is
now a fix in the 2021.07 release. It is on GitHub now. It will be on OSVVM.org
I have plans to work on the regression scripting so we will have a summary of pass/fail
on all tests coming out of the regression suite.
Thanks for the issue report. My goal is to have OSVVM working on all VHDL simulators.
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