Hi Alpha,
The Axi4Memory supports the full capability of the AXI4 bus from the DUT side interface – including a multi-beat burst. This allows the DUT to interact with any addressable location in the memory. Be careful to keep your address space reasonable as the Axi4Memory creates a data structure and sizes above 2**40 are not currently supported. We start throwing warnings at 2**34 bits of memory as this seems to slow some simulators down.
The Axi4Subordinate (separate VC) does not support bursting. This VC is intended to emulate a register based subordinate – which generally do not support bursting.
Page 30 describes the transaction interface to the Axi4Memory that allows the test sequencer (TestCtrl) to access the memory also. This interface is not about talking to your DUT. Instead it gives TestCtrl a back door into the memory model and allows it to introspect the contents of memory. These accesses complete in a couple of delta cycles – be careful about doing too many consecutively without time passing as you can hit the delta cycle iteration limit.
I will look at updating the documentation to clarify this.