Using WaitForTransaction/RequestTransaction in a testbench

[Francois]

I have implemented testbenches using OSVVM for a while now, but only on very simple components. I am now investigating using the full OSVVM framework to manage more complicated DUTs. I created a test environment to train myself on using VCs and implementing a test sequencer, but ran into a problem where I get the error:

** Error: ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(36): Nonresolved signal ‘ManagerRec’ has multiple sources.

It seems like that my method is similar to you implementation using the DpRam testbench as an example.

How did you get past this problem?

Here is my test harness:

LIBRARY ieee;
use IEEE.std_logic_1164.all;
  use IEEE.std_logic_1164.all;
  use ieee.numeric_std.all ;
  use ieee.numeric_std_unsigned.all ;

library osvvm ;
  context osvvm.OsvvmContext ;

library work;
  use work.OsvvmTestCommonPkg.all ;
  use work.CounterTransactionPkg.all ;

entity counter8_tb is
end entity counter8_tb;

--
architecture test_harness of counter8_tb is
  constant tperiod_Clk  : time := 10 ns ;
  constant tpd          : time := 2 ns ;

  signal Clk            : std_logic ;
  signal nReset         : std_logic ;
  signal CntEn          : std_logic;
  signal Counter        : STD_LOGIC_VECTOR(7 downto 0);
  
  signal ManagerRec     : CounterRecType;
  
  -- Component declarations
  component counter8
    port (
      Clk     : in     STD_LOGIC;
      nRst    : in     STD_LOGIC;
      CntEn   : in     STD_LOGIC;
      Counter : out    STD_LOGIC_VECTOR(7 downto 0)
    );
  end component counter8;
  
  component TestCtrl is
    Port (
      Clk      : in  STD_LOGIC;
      TransRec : inout CounterRecType
    );
  end component TestCtrl;
  
begin

  -- create Clock
  Osvvm.ClockResetPkg.CreateClock (
    Clk        => Clk,
    Period     => Tperiod_Clk
  );
  
  DUT : counter8
    port map (
      Clk     => Clk,
      nRst    => nReset,
      CntEn   => CntEn,
      Counter => Counter
    );
    
  CounterCtrl : CounterController
    port map (
      Clk       => Clk,
      nRst      => nReset,
      CntEn     => CntEn,
      Counter   => Counter,
      TransRec  => ManagerRec
    );

  TestCtrl1 : TestCtrl
    port map (
      Clk       => Clk,
      TransRec  => ManagerRec
    );

end architecture test_harness;

The script to build it all:

library osvvm_tb_demo_lib

analyze  OsvvmTestCommonPkg_pkg.vhd
analyze  CounterTransactionPkg.vhd

analyze TestCtrl_e.vhd
analyze CounterController_rtl.vhd
analyze counter8_tb_test_harness.vhd
analyze TestCtrl_BasicCount.vhd

RunTest TestCtrl_BasicCount.vhd

[Jim Lewis]

Hi Francois,
The VC in the OSVVM library use either osvvm_common.StreamTransactionPkg.StreamRecType (for send and get type transactions – used by UART, AxiStream, xMii) or osvvm_common.AddressBusTransactionPkg.AddressBusRecType (for read and write type transactions – used by Axi4Manager, Axi4Memory, DpRam, WishboneManager, WishboneSubordinate).

You can access either one using
`
library osvvm_common ;
context osvvm_common.OsvvmCommonContext ;
`

A testbench for a counter may only need directive transactions, for which either record will work.
You can create your own record. Use those packages as an example if you like.

Best Regards,
Jim

[Francois]

Hi Jim,

I did create my own record:

type test_command_type is (AssertResetCmd, DeassertResetCmd, AssertEnableCmd, DeassertEnableCmd, RunCounterCmd, StopCounterCmd, ReadCounterCmd, DoneCmd);
    
  type CounterRecType is
  record
    rdy     : RdyType;
    ack     : AckType;
    cmd     : test_command_type;
    counter : STD_LOGIC_VECTOR(7 downto 0);
  end record CounterRecType;

However, I keep running into this error:

# -- Compiling entity counter8_tb
# -- Compiling architecture test_harness of counter8_tb
# ** Error: ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(39): Nonresolved signal 'ManagerRec' has multiple sources.
#   Drivers:
#     ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(83):Instantiation TestCtrl1
#     ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(74):Instantiation CounterCtrl
# ** Note: ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(89): VHDL Compiler exiting

You do the same in OsvvmLibraries/DpRam/testbench/TbDpRam.vhd with signals Manager1Rec and Manager2Rec. However, your testbench does not generate the same error.

I cannot figure out what you are doing differently not to generate this error.

Regards,

Francois

[Author]

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