Joseph

Thanks for the info Jim! I was dealing with some unusual sizes for logic vectors. So, I just resized them in my VC to have a bigger width to capture all of the data since I actually wanted to capture all of the data bits, not just some of them. I now don’t get this error anymore.

This is resolved now. The problem was I was calling the VC directly instead of WRITE or READ, which calls the operations in my VC.

Hi Jim,

Thanks for the speedy reply. I can’t post the DO file, but I can try to post the what it is supposed to do. This test bench passes vector files which poke around registers. The vector files use a custom API that my team developed that go through a VHDL file to a VHDL test bench. It is based on OSVVM, but there’s the extra layer from our…[Read more]

I have a test bench that is run from a DO file. It is based on OSVVM. We were wanting to add code coverage, so I was looking into making a PRO file with the settings SetCoverageAnalyzeEnable and SetCoverageSimulateOptions set to true. But I’m not sure how to run the DO file in that PRO file. I’m relatively new to OSVVM, so any input is…[Read more]