Mikael
-
Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 3 weeks ago
The Report APIs should be there in Questa sim 2025.2.
The latest Questasim version is now 2025.3Remember that today, mixed language designs are very common. Some IPs are only available in Verilog.
So it is not just VHDL assertions that can be a source of errors.
There could be SVA assertions, both immediate and concurrent.IPs or library…[Read more]
-
Mikael replied to the topic Safer Check if Simulation passed or Not in the forum OSVVM 3 weeks, 1 day ago
By saving the UCDB file for each testcase (<testname>.ucdb , you can also check the teststatus afterwards:
>vcover attribute OsvvmTemp_Questa/TbAxi4_DemoMemoryReadWrite1.ucdbThe tcl procedure I use to check the test status,just contact me and I will send it. Seems like the code is blocked.
-
Mikael started the topic Safer Check if Simulation passed or Not in the forum OSVVM 3 weeks, 1 day ago
Today the outcome of the simulation is solely dependent on the OSVVM report server and if you have triggered an error or not.
But if you have for example an external library cell/ip that uses assertions, it can still look as the simulation passed while it indeed failed.I added “assert false” in a testcase to illustrate the problem. This is the…[Read more]
-
Mikael became a registered member 3 weeks, 1 day ago
