Regarding topic 2) I think there is a problem with that specific version Questa/ModelSim 2019.2, but I don´t know exactly a reason.
Try another version (previous or later).
Thanks for nice post, it is quite useful.
I have a few comments:
1. If we want fewer lines of the code, we can combine Bins using concatenation &, for example :
GenBin(BlackJack_type’POS(BustState)) & GenBin(BlackJack_type’POS(HoldState)) &…[Read more]
Miroslav Marinkovic replied to the topic Question to the OSVVM community: how to approach the methodology, learning curve in the forum OSVVM 3 years, 8 months ago
Regarding your question 3):
First, you mentioned that your current VHDL testbenches write output data into a file, and then you process (offline) the obtained data vs. reference data.
In my opinion, it is better to compare output data vs. reference data directly in VHDL testbench, because you have a self-checking testbench in that…[Read more]