Thanks for your reply.
as I thought, there is NO other way of doing it Without MODs to DUT
This Rules out generated Code.
So VHDL Needs Fixing
The most Flexible Fix would be:-
ALIAS FSM_STATE_TYPE_HANDLE is \<\<TYPE DUT.FSM_STATE_Type : NULL\>\>;
ALIAS FSM_STATE_HANDLE is \<\signal DUT.FSM_STATE : INCOMPLETE_Type_Name\>\>;
Would be OK
I won’t hold my breath for the next Version of VHDL.
In the Meantime I’ll use a Duplicate Type Declaration because ModelSim accepts it even though IT SHOULDN’T.
The Double Greater than or Less than Chars used for External Names Really seem to mess up Forum Posts so I Put a \ in front of them.
You may Find this Useful
Had a ReThink about OSVVM Temporal Coverage.
Can we do it with the existing Packages?
YES WE CAN!
RandCovPoint produces Numbers & we can let those Numbers represent whatever we want.
We can let those Numbers represent TIME if we want to.SOWe do not need new Packages to do OSVVM Temporal Coverage.
See this posthttps://osvvm.wpengine.com/forums/topic/intelligent-temporal-coverage-with-osvvm
Yes, I DownLoaded your ScoreBoarding Pkg weeks ago but I haven’t used it for real yet.
When I discovered OSVVM a couple of years ago, I STOPPED USING most of my verification Packages & decided to use OSVVM INSTEAD.
The effort I put into my Packages was just enough for what I needed & NO MORE.I simply don’t have time to do what you have done.
OSVVM is a BIG time saver.
JimThanks for your very rapid reply.
What can we do if we want AT LEAST VALUES on a diagonal to be legalBUTHIGHER than the rest.
Is it still possible to do the diagonal seperately in a simple loop similar to above.