Activity – Veit – Open Source VHDL Verification Methodology

Veit replied to the topic Confusion of Axi4Full Testcases in the forum OSVVM 1 month, 2 weeks ago

Found 2 more cases (checking currently only AXIFull):
TbAxi4_MemoryBurstAsyncPattern2.vhd:
architecture name: MemoryBurstAsyncPattern1

TbAxi4_MemoryReadWriteDebug1.vhd:
architecture name: MemoryReadWrite1 (debug missing)

Veit started the topic Confusion of Axi4Full Testcases in the forum OSVVM 1 month, 2 weeks ago

Hi,
with my marriage (see “https://osvvm.org/forums/topic/using-vcs-without-the-built-in-scripts”) of OSVVM and VUNIT I found a confusion in the TbAXI4_[AXI?]ManagerRandomTiming Testcase:

——————————————————-
TbAxi4_ManagerRandomTiming1 :
architecture: ManagerRandomTiming1
…
Configuration…[Read more]

Veit replied to the topic Using VCs without the built-in Scripts – but instead VUnit in the forum OSVVM 1 month, 2 weeks ago

prev post, drawing

Veit replied to the topic Using VCs without the built-in Scripts – but instead VUnit in the forum OSVVM 1 month, 2 weeks ago

Hi all,
I’m a rooky regarding OSVVM.

But now my marriage of OSVVM and VUNIT for the AXI testsuite seems to run (2 TCs fails currently, and I need a deeper invest). But i needed some changes.

Vunit runs all TCs in a single step, so I needed to install all TestCases parallel.

A one-hot from the vunit testbench (the runner process) selects the…[Read more]

Veit

@simarillon