Upcoming OSVVM Events

October 18, 2015 in Event

OSVVM Presentation in Copenhagen
IDA is hosting an OSVVM presentation on 9 November 2015 from 18:30 til 20:30.  For details see:  http://ida.dk/event/316127

OSVVM and Error Reporting
DVCon Europe in Munich, Germany.  See:  DVCon-Europe Program

OSVVM World Tour Training Dates
VHDL Testbenches and Verification – OSVVM+ Boot Camp
Learn the latest VHDL verification techniques including transaction level modeling (tlm), self-checking, scoreboards, memory modeling, functional coverage, directed, algorithmic, constrained random, and intelligent testbench test generation. Create a VHDL testbench environment that is competitive with other verification languages, such as SystemVerilog or ‘e’. Our techniques work on VHDL simulators without additional licenses and are accessible to RTL engineers.

November 16-20 Copenhagen, Denmark Enroll with FirstEDA
November 30 – December 4 and December 14-18 online class Enroll with SynthWorks
January 11-15 and January 25-29 online class Enroll with SynthWorks
February 1-5 Bracknell, UK Enroll with FirstEDA

Presented by:
Jim Lewis, SynthWorks VHDL Training Expert, IEEE 1076 Working Group Chair, and OSVVM Chief Architect

2 responses to Upcoming OSVVM Events

  1. Good to see, that OSVVM is present at the DVCon between all this other UVM stuff.

    A question to your training schedule: Are there any plans to hold a training in Germany next year? It’s difficult to get foreign training courses approved in our company.

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