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Founders of OS-VVM
Aldec is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs.
With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.
SynthWorks provides training in leading edge VHDL verification techniques, including transaction based testing, bus functional modeling, self-checking, data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random, and coverage driven random testing, and functional coverage.
VHDL Analysis and Standardization Group (VASG) is responsible for maintaining and extending the VHDL standard (IEEE 1076).
P1076 is an individual based standard. Participation is not just your right, if you are a senior member of the VHDL community, it is your obligation – otherwise, the only one you can blame for not having the new features you want is you. The only requirement for membership is to show up and participate. Work is done via on the email reflector, TWIKI site, and in our phone meetings. Opportunities to participate are available at many different levels of commitment and your participation will help.