Announcing OSVVM 2020.05

Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).

OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC.

According to the 2018 Wilson Verification Survey, OSVVM is the #1 VHDL Verification Library in the world, and in Europe, OSVVM is the #1 FPGA Verification library (ahead of SystemVerilog + UVM).

Error reporting and messaging is an important part of any testbench. One of the features added in the 2020.05 release is the ability to track PASSED conditions throughout the OSVVM error reporting and messaging data structure (in AlertLogPkg).

This means that when a test completion report is created by ReportAlerts, the number of Passed conditions for each AlertLogID in the hierarchy is reported. By default, it will produce a report similar to the following. Note, each line starts with “%%”.

%% DONE  FAILED  Axi4_Uart1  Total Error(s) = 7  Failures: 0  Errors: 7  Warnings: 0  Passed: 8  Affirmations Checked: 14  at 380810 ns
%%    Default                Failures: 0  Errors: 0  Warnings: 0  Passed: 0
%%    OSVVM                  Failures: 0  Errors: 0  Warnings: 0  Passed: 0
%%    TB                     Failures: 0  Errors: 2  Warnings: 0  Passed: 2
%%    AxiMaster              Failures: 0  Errors: 3  Warnings: 0  Passed: 0
%%      AxiMaster: Protocol  Failures: 0  Errors: 1  Warnings: 0  Passed: 0
%%      AxiMaster: Checker   Failures: 0  Errors: 2  Warnings: 0  Passed: 2
%%    UartTx                 Failures: 0  Errors: 0  Warnings: 0  Passed: 2
%%    UartRx                 Failures: 0  Errors: 2  Warnings: 0  Passed: 2

Here Passed indicates what items have passed and Affirmations indicates the number of checks that have been done. AxiMaster, UartTx, and UartRx are the names of the separate Verification IP doing the reporting.

When a test passes, the number of passed and affirmations will be then same.

%% DONE  PASSED  Axi4_Uart1  Passed: 14  Affirmations Checked: 14  at 380810 ns

You can disable the passed messages printed for each model by:
SetAlertLogOptions(PrintPassed => DISABLED);

When OSVVM introduced AlertLogPkg, error reporting and messaging capability (aka logging) had already become a common capability in programming languages. However, we also required model based reporting – something that did not exist in VHDL at the time, so we wrote our own. Our big goal was to make both simple reporting as well as model based error reporting and messaging easy. How did we do?

For more on the OSVVM AlertLogPkg, see the AlertLogPkg User Guide on GitHub.

OSVVM 2020.05 also includes updates to OSVVM’s ScoreboardGenericPkg and CoveragePkg. For additional details see the osvvm_release_guide for 2020.05 on GitHub.

Download the release from GitHub or the OSVVM downloads page.

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