VHDL+OSVVM vs SystemVerilog+UVM

VHDL + Open Source VHDL Verification Methodology (OSVVM) is great for verification and is a competitor to SystemVerilog + UVM. Especially in the FPGA space where VHDL is the dominant language (see the 2020 Wilson Verification Survey).

Some refute this claiming that, “VHDL falls flat on its face when used for verification” and “VHDL can do a lot, however, it cannot do everything SystemVerilog does since it is missing inheritance, constraints, and a constraint solver.”

Lets be fair. To learn SystemVerilog it probably took a considerable amount of study and/or a training class to learn the SystemVerilog patterns for verification. So you need to do the same with VHDL+OSVVM, however, don’t worry as for VHDL users OSVVM is easier (and if you need training, we have you covered).

We also need to focus on what we need: verification capability. Language features, such as inheritance, constraints, and constraint solvers are just tools and provide one way to implement a particular verification capability. So you may not see a way to solve a verification capability with VHDL using SystemVerilog patterns. That is ok. However, it is not ok to then conclude, VHDL cannot do it. In OSVVM, we solve the same verification problem using different methods.

For example, in a recent post someone made the claim that VHDL+OSVVM cannot, “Create tests for a complex, packet based protocol with relationships between different fields.”

With OSVVM, it is just programming and here are the steps:

Step 1:

Start by writing a functional coverage model (cross coverage in this case) that tracks the different combinations of protocols and field values that need to happen to satisfy the test plan.

OSVVM functional coverage is modeled in sequential code, incrementally at time 0. Conditional coverage based on a generic, no problem. Passing in a coverage model or partial coverage model as a generic or a constant also no problem. Hence, writing high fidelity (exact) cross coverage models is just a matter of writing the code.

Step 2:

Do a random walk across the coverage model – aka – randomly select a coverage bin that has not reached its coverage goal yet. Since the coverage model describes the inputs we want to generate, the randomization selects the next stimulus set (protocol and different fields) to do.

Coverage goals for each individual bin in the coverage model can be set when capturing the coverage. A bin will be randomly selected until its coverage goal has been reached. Hence, if one sequence needs to be generated more frequently than another, set its coverage goal to a higher value. This allows us to do things like send 75% of the packets to the ethernet switch port that is designated to be the file server.

If you follow Brian Bailey, he once described Functional Coverage and Randomization constraints as two views of the same thing, and hence, you only need one. Here OSVVM only uses one – Functional Coverage. SystemVerilog uses both.

Lets see, how did OSVVM do here with respect to SystemVerilog?

Less work because here we did not have to write randomization constraints.
Minimized or no redundant stimulus.
No performance degradation due to a constraint solver.
Looks like VHDL+OSVVM capability came out ahead of SystemVerilog+UVM capability in implementing this problem.

OSVVM has been busy all summer doing formal releases in June, July, and September. You can get these releases at osvvm.org or github. OSVVM has made some significant advances with verification data structures that I will be talking about over the next several blog posts – spoiler – the user API for the data structures has been simplified, while at the same time we maintained backward compatibility – because as a member of the VHDL standards working group the “Prime Directive” is do not break old code.

We have also made some significant advances with tool support that we will be announcing in the near future.

Looking forward, we have great plans for our fall/winter projects that will bring us further into par with SystemVerilog tools.

Looking for a great class, see Advanced VHDL Testbenches and Verification – OSVVM Boot Camp.

Be sure to like the LinkedIn version of this post.