AMD XSIM 2023.02: On the Road to OSVVM

Quite some time ago I tried out AMD/Xilinx XSIM in OSVVM. Unfortunately at the time, it was like the Talking Heads song – “We’re on a road to no where”

Things have changed. We have heard good things about Vivado Synthesis starting to support VHDL-2019 features – like interfaces. Hear that Siemen’s? Are you going to let AMD Vivado pass you as well as Aldec?

So my holiday project was to try out XSIM again. The road started with elaboration errors like:

ERROR: [XSIM 43-3294] Signal EXCEPTION_ACCESS_VIOLATION received.
…
Error: child killed: segmentation violation

Errors of this sort are not like normal tool errors that give you a line number and then you can go search on Reddit or StackOverflow for a solution. They are more like the simulator gives a curious message during its last gasp for air and then dies.

This seems like a hopeless road block, however, my brave parrot (my live substitute for a rubber ducky) and I started out on this journey and we were determined to find out what does and does not work in XSIM.

When a design does not elaborate, I start by commenting out all the suspicious code – sometimes all of the code is suspicious – and then try to load the simulation. If elaboration fails, I comment out more – such as declarations or other code. If it loads without elaboration errors then I uncomment half of the code and try again. I repeat this binary search pattern until the issue or issues are uncovered – sometimes there is more than one issue in a path. Once I have identified the issues, then I try alternative code for the issue – often we can find something that does work.

Using this process I gently convinced XSIM that together we could work through its issues. The results are promising.

• Working: Osvvm Utility Library (library osvvm) with work arounds – except for the resolved types in ResolutionPKg.
• Working: Scripting. Libraries currently go to a default directory – we have some work to get them to a specified directory. Log files need some work – we need TCL 8.6 for full capability, XSIM has TCL 8.5.
• Has Issues: OSVVM Streaming VC (UART, AxiStream, Ethernet) require work arounds in user test cases and testbench.
• Has Issues: The OSVVM Address Bus VC (Axi4Full, Axi4Lite, DpRam, …) still need work. DpRam runs but information does not flow through the transaction record correctly.

 
Xilinx updates are in the OsvvmLibraries main branch on GitHub.

I am looking forward to reconnecting with my Xilinx contacts in the New Year and eliminating the issues.