XSIM Loves OSVVM

I am often asked does OSVVM work in XSIM? With the upcoming OSVVM 2025.02 release – YES!!!

As I was wrapping up on OSVVM 2025.02 release, inspired by another instance of this question, I decided to take a look at XSIM 2024.2.

Status

At first look, XSIM 2024.2 looked like two steps backward from XSIM 2023.2.

Within the OSVVM Utility library (library osvvm), MemoryPkg – which was updated to work with XSIM 2023.2 – was crashing XSIM 2024.2 and had to be updated again. TextUtilPkg also had some minor updates.

There are some minor issues in the OSVVM Utility library that could not be worked around. InitSeed from RandomPkg with a time parameter does not work since std.env.resolution_limit in XSIM returns 0. Resolution functions do not work with types real or time in XSIM. This means that VC that need to have an option that uses a time value, such as setting UART baud rate will not currently work. Fortunately, these are very minor issues.

Minor updates were made to OSVVM scripting to get the reports to work properly in XSIM. XSIM 2024.2 supports tcl 8.6. A result OSVVM is now able to produce proper log files in XSIM rather than the work-around we had with 2023.2.

AXI4 Full and AXI4 Lite VC needed minor updates. However, following these updates the VC work without needing a special Xilinx version.

Congratulations to the XSIM development team.

An early version of OSVVM 2025.02 is available on the OsvvmLibraries Dev GitHub branch. I expect a formal release of 2025.02 to happen shortly.
 

Why OSVVM?

Open Source VHDL Verification Methodology (OSVVM) is a suite of libraries designed to streamline your entire VHDL verification process, boosting productivity and reducing development time. OSVVM rivals the verification capabilities of any other verification methodology – including SystemVerilog + UVM. A brief list of these capabilities include:

• A structured, transaction-based testbench approach that is suitable for all verification tasks – from Unit/RTL to full chip/system level testing.
• Test cases and verification components that can be written by any VHDL Engineer.
• Test cases that are readable and reviewable.
• Test case and requirements reports in HTML to facilitate debug and test artifact collection.
• Support for continuous integration (CI/CD) reporting.
• Powerful and concise verification capabilities including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.
• A Co-simulation capability that supports running software (C++) in a hardware simulation environment.
• Simulator support includes GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, Cadence Xcelium and AMD/Xilinx XSIM.
• Scripting that is as simple as a list of files and is portable between simulators. This facilitates using an open-source simulator for regression testing.
• A Model Independent Transaction (MIT) library that simplifies writing verification components and test cases.
• Unmatched reuse through the entire verification process.

Upcoming OSVVM Classes

 
Class details are at Advanced VHDL Testbenches and Verification – OSVVM™ Boot Camp.
Although PLC2 uses a different course title, the materials are the same.

SynthWorks’ on-line classes are instructor led, “half day” class sessions. For more details see
On-line class details.