Activity – Open Source VHDL Verification Methodology

Jim Lewis replied to the topic Cannot compile the library with Modelsim 10.5b in the forum OSVVM 8 years, 4 months ago

I test with QuestaSim 10.5b so if you have the compile order correct, you should be fine.How did you compile it? Did you use the osvvm.do file? See: https://github.com/OSVVM/OSVVM/blob/master/osvvm.doDid you use the directions in the OSVVM_release_notes.pdf? See: https://github.com/OSVVM/OSVVM/blob/master/doc/osvvm_release_notes.pdfI note…[Read more]
Jim Lewis replied to the topic Limitation using MemoryPkg in the forum OSVVM 8 years, 5 months ago

Hi Eilert,In the 2008 standard it says:An implementation shall choose a representation for all floating-point types except for universal_real that conforms either to IEEE Std 754-1985 or to IEEE Std 854-1987; in either case, a minimum representation size of 64 bits is required for this chosen representation.I think this changed before 2008,…[Read more]
Eilert Backhus replied to the topic RandomPkg: How to set weight for range in the forum OSVVM 8 years, 6 months ago

Hi Jim,I hoped that there’s some solution using the range notation like you showed:With named association, you can also do the following:
A <= RndA.DistSlv((0=>5, 1 to 14 =>1, 15=>5), A'length) ;I just didn’t expect it to be so straight simple, since the defined type is self defined. You mentioned integer_vectors somewhere else. Are these…[Read more]
Jim Lewis replied to the topic Reporting ignored bins in the forum OSVVM 8 years, 6 months ago

Hi Roger,I just did a code review regarding AtLeast. Looking at the code, the AtLeast value is the maximum of the one specified by AddBins (the way I usually show to enter it) and the value specified by GenBin (also specified by a first integer value – but then also requires at least 4 parameters be used). Hence, if you specify both, you may be…[Read more]
Jim Lewis wrote a new post 8 years, 9 months ago

I am getting ready for the next session of Advanced Testbenches and Verification in UK and am looking forward to meeting another group of students.
Ready to improve your VHDL verification methodology? Come join […]
Jim Lewis replied to the topic Scoreboard Package Error in Questa in the forum OSVVM 8 years, 10 months ago

That unfortunately is a known bug. 10.4 brought some new cool features, but some how broke for the scoreboard in a way that I could not figure out how to work around. If you are just working with the primary releases, the following versions also exhibit the issue: 10.4, 10.4a, 10.4b, 10.4c. 10.3 was fine. 10.4d and 10.5 are fine. The…[Read more]
Jim Lewis replied to the topic Possible Error in "ScoreboardPkg User Guide.pdf" in the forum OSVVM 8 years, 10 months ago

Good catch. I updated the source document. Thanks.
Jim Lewis wrote a new post 9 years, 1 month ago

2016.11a is a minor release. The only file that changed is VendorCovApiPkg_Aldec.vhd. There was a bug in one of the attributes that has been fixed and verified.
VendorCovApiPKg simplifies the connection […]
Mark replied to the topic Problems? Suggestions? in the forum OSVVM 9 years, 11 months ago

When using ReadLogEnables to select what logging is enabled any logs that are enabled descend down the hierarchy. As you can only set not disable logs in a file this means that I can’t enable logging near the top of my hierarchy without this pushing all the way down to the bottom.Would it be possible to change the ReadLogEnables so that it only…[Read more]
Jim Lewis wrote a new post 10 years, 3 months ago

OSVVM Presentation in Copenhagen
IDA is hosting an OSVVM presentation on 9 November 2015 from 18:30 til 20:30. For details see: http://ida.dk/event/316127
OSVVM and Error Reporting
DVCon Europe in Munich, […]
Ralf replied to the topic Standard messaging feature in OSVVM? in the forum OSVVM 11 years, 7 months ago
Steve Chan started the topic PSL or SVA? in the forum VHDL 12 years, 11 months ago

*Hi allI am planning to start embedding the more advance assertion contruct in my HDL/TestBench design.My company is generally a VHDL house, but I can foresee use of SV in the future.A mixed language environment is very likely to happen (as a matter it already exist)I have read either PSL or SVA can work in both SV and VHDL.So which assertion…[Read more]
Jim Lewis wrote a new post 13 years, 1 month ago

Why no constraint solver? Are you going to add one?Nope. No constraint solver. Instead OS-VVM implements an innovative “Intelligent Testbench” feature that does a random walk across functional cove […]
vio123 started the topic ../packages/RandomPkg.vhd(92): Range 0 downto 1 is null in the forum OSVVM 13 years, 1 month ago

Hi all,from RandomPkg.vhd ref.: 2.1* constant NULL_INTV : integer_vector (0 downto 1) := (others => 0);Modelsim gives ** Warning: [3] ../packages/RandomPkg.vhd(92): (vcom-1246) Range 0 downto 1 is nullNULL_INTV is used as init value, but why with this empty range ?Bug, Feature ?
Steve Chan started the topic How to compare compare std_logic and integer in the forum VHDL 13 years, 3 months ago

Hi expertA supposing easy question.How to easily compare std_logic to integer of 0 and 1 without using “complex” “if then else” kind statement?I was trying to find use assert to compare the std_logic and the input vector in integer.Thanks
Brian Padalino started the topic Coding/Naming Conventions in the forum OSVVM 13 years, 8 months ago

I recently downloaded the OSVVM package and was looking it over. Something that was striking was the naming conventions in the packages which seemed, to me, somewhat inconsistent.For an example, I am looking at RandomPkg.vhd in the package declaration. One observation is that VHDL is insensitive to case, so DISTTYPE is the same as DistType.…[Read more]
Jim Lewis started the topic RandCovPoint(0.0) and potential changes in the forum OSVVM 13 years, 9 months ago

Hi,This post is to discuss a planned change to RandCovPoint. Its current declaration is:impure function RandCovPoint ( PercentCov : real := 100.0 ) return integer_vector ;Currently PercentCov is used to enable two separate concepts. If PercentCov is greater the current minimum coverage, then PercentCov represents a coverage goal. Anything…[Read more]
kuri started the topic About cyclic randomlike the randc of SystemVerilog in the forum OSVVM 13 years, 9 months ago

Hi,Can the cyclic random like the randc of SystemVerilog be described in OS-VVM?I think that I describe it by using the function coverage and RandCovPoint method.Is this idea correct?best regards,kuri
Ian Gibbins started the topic How to handle protected types in the forum VHDL 13 years, 9 months ago

I see that OS-VVM is using protected types internally at the quite advanced level. I have done my share of coding in VHDL but am not very familiar with this type of construct. Any suggestions how to improve my understanding?