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Modimo became a registered member 9 months ago
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Amr became a registered member 9 months ago
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sunilkumar became a registered member 9 months ago
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Andy became a registered member 9 months ago
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Will became a registered member 9 months, 1 week ago
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Berkeley became a registered member 9 months, 1 week ago
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Jim Lewis started the topic CreateClock moved to ClockResetPkg in 2024.07 in the forum OSVVM 9 months, 1 week ago
In 2024.07, CreateClock (and CreateReset) moved from TbUtilPkg to ClockResetPkg. This was done to separate the dependencies that are needed from the low level synchronization primitives from the higher level CreateClock (and the checkers that check the clock period and reset).
If you had a reference to CreateClock using a selected name as…[Read more]
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Bobo became a registered member 9 months, 1 week ago
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Jim Lewis replied to the topic Error on running a script twice in the forum OSVVM 9 months, 1 week ago
Hi Preston,
What version are you running? Did the previous build fail?Prior to 2024.07, if an include failed, there were some conditions under which it would not restore the CurrentWorkingDirectory back to the original value. This was addressed in 2024.07. This only happened if something in the process used an exit code that indicated a…[Read more]
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Preston started the topic Error on running a script twice in the forum OSVVM 9 months, 1 week ago
Hi,
I’ve encountered an error after running a .pro script once (a test runs and completes), and then trying to run it again. This is the error output from Riviera-Pro (had the same issue come up in Modelsim):
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build ../tests/osvvm_testcases/RunAllTests.pro
# Error: Build…[Read more] -
Hassan replied to the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL 9 months, 2 weeks ago
In the VHDL as it exists today, we must use numeric_std. No arithmetic is thus possible with std_logic_vector, we must use signed or unsigned.
I do not understand, what logic or arithmetic principle is broken when signed is converted to std_logic_vector implicitly or unsigned is converted to std_logic_vector implicitly.
I am merely talking about…[Read more]
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Hassan replied to the topic Convert std_logic_vector to record in the forum VHDL 9 months, 2 weeks ago
I am just wondering how come the big names like Siemes, Mentor Graphics e.t.c don’t fund this group. Also, the government does not seem to show any keen interest to fund this. The evolution of technology requires tools to be in place. If the industry giants don’t come together to make it happen, who else is going to make it happen?
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Jim Lewis replied to the topic Convert std_logic_vector to record in the forum VHDL 9 months, 2 weeks ago
Yes it should have more regular updates. However to do that we need more volunteers and/or funding for the people who do the work.
Personally, I put in 1000+ hours of my own time into VHDL-2019. I cannot afford to do that amount of uncompensated time in the future.
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Jim Lewis replied to the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL 9 months, 2 weeks ago
Like types integer and real, the types signed, unsigned, and std_logic_vector are different types.
One really cool thing about different types is they support independent overloading, hence, the “+” operator for signed is unique and different from the “+” operator for unsigned. If they automatically converted this would not be possible.
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Nestor became a registered member 9 months, 2 weeks ago
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Jim Lewis wrote a new post 9 months, 2 weeks ago
OSVVM release 2024.07 + Conference Trip ReportIt seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three […]
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Hassan started the topic VHDL port map between std_logic_vector(0 downto 0) and std_logic in the forum VHDL 9 months, 2 weeks ago
When using generics to control data width of ports we could end up with std_logic_vector(0 downto 0) due to the data width being 1. When connecting this to an std_logic signal there is always an error of mismatch since there is std_logic_vector(0 downto 0) on on side and std_logic on the other side.
The way to deal with this issue is to do this…[Read more]
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Hassan replied to the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 9 months, 2 weeks ago
Thanks.
My question is actually about synthesizeable code rather than simulation and thus I have put it under VHDL rather than OSVVM.
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Jim Lewis replied to the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 9 months, 2 weeks ago
Hi Hassan,
For the OSVVM MemoryPkg, see FileReadH and FileReadB as well as their counter parts FileWriteH and FileWriteB.For simulation based RAMS, you want to be using OSVVM’s MemoryPkg as it creates sparse memory data structures – ie it only allocates blocks of memory (in 1 K chunks) if you write to a particular location.
Best Regards,
Jim -
Hassan started the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 9 months, 2 weeks ago
Verilog/SystemVerilog (synthesis) has some functions that can read a file into a signal. These are $readmemb and $readmemh. These can both be used to easily create a ROM from file contents. As far as I know, VHDL does not contain anything along these lines that will work in synthesis. Is this true? If so, why is this so?
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