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In the VHDL as it exists today, we must use numeric_std. No arithmetic is thus possible with std_logic_vector, we must use signed or unsigned.

I do not understand, what logic or arithmetic principle is broken when signed is converted to std_logic_vector implicitly or unsigned is converted to std_logic_vector implicitly.

I am merely talking about…[Read more]

I am just wondering how come the big names like Siemes, Mentor Graphics e.t.c don’t fund this group. Also, the government does not seem to show any keen interest to fund this. The evolution of technology requires tools to be in place. If the industry giants don’t come together to make it happen, who else is going to make it happen?

Yes it should have more regular updates. However to do that we need more volunteers and/or funding for the people who do the work.

Personally, I put in 1000+ hours of my own time into VHDL-2019. I cannot afford to do that amount of uncompensated time in the future.

Like types integer and real, the types signed, unsigned, and std_logic_vector are different types.

One really cool thing about different types is they support independent overloading, hence, the “+” operator for signed is unique and different from the “+” operator for unsigned. If they automatically converted this would not be possible.

Thanks.

My question is actually about synthesizeable code rather than simulation and thus I have put it under VHDL rather than OSVVM.

Hi Hassan,
For the OSVVM MemoryPkg, see FileReadH and FileReadB as well as their counter parts FileWriteH and FileWriteB.

For simulation based RAMS, you want to be using OSVVM’s MemoryPkg as it creates sparse memory data structures – ie it only allocates blocks of memory (in 1 K chunks) if you write to a particular location.

Best Regards,
Jim

If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:

#if FEATURE1

#endif

#if FEATURE2

#if FEATURE3VER > 2

#else

#endif

#endif

How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be…[Read more]

One more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than…[Read more]

Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.

For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/

VHDL in particular is a volunteer driven standard. Hence, it is…[Read more]

2024.07 updates CreateClock. They are breaking changes – meaning the way clock starts up is different. There was alot of unneeded complexity that was part of the old CreateClock that has been minimized – while still keeping clock changing at simulation cycle 0 (aka delta cycle 0).

If you want to preview it, see the Dev branch. Nominally it…[Read more]