Activity
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Nestor became a registered member 9 months, 3 weeks ago
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Jim Lewis wrote a new post 9 months, 4 weeks ago
OSVVM release 2024.07 + Conference Trip ReportIt seems like yesterday that I got back from Verification Futures Conference (June 18) and FPGA Conference Europe (July 2-4) – but it is actually been three […]
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Hassan started the topic VHDL port map between std_logic_vector(0 downto 0) and std_logic in the forum VHDL 10 months ago
When using generics to control data width of ports we could end up with std_logic_vector(0 downto 0) due to the data width being 1. When connecting this to an std_logic signal there is always an error of mismatch since there is std_logic_vector(0 downto 0) on on side and std_logic on the other side.
The way to deal with this issue is to do this…[Read more]
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Hassan replied to the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 10 months ago
Thanks.
My question is actually about synthesizeable code rather than simulation and thus I have put it under VHDL rather than OSVVM.
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Jim Lewis replied to the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 10 months ago
Hi Hassan,
For the OSVVM MemoryPkg, see FileReadH and FileReadB as well as their counter parts FileWriteH and FileWriteB.For simulation based RAMS, you want to be using OSVVM’s MemoryPkg as it creates sparse memory data structures – ie it only allocates blocks of memory (in 1 K chunks) if you write to a particular location.
Best Regards,
Jim -
Hassan started the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 10 months ago
Verilog/SystemVerilog (synthesis) has some functions that can read a file into a signal. These are $readmemb and $readmemh. These can both be used to easily create a ROM from file contents. As far as I know, VHDL does not contain anything along these lines that will work in synthesis. Is this true? If so, why is this so?
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David became a registered member 10 months ago
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Hassan started the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL 10 months ago
The signed, unsigned and std_logic_vector are all ultimately based on the std_logic. Why does VHDL require explicit conversion from signed to std_logic_vector and unsigned to std_logic_vector?
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Hassan replied to the topic The #if in VHDL in the forum VHDL 10 months ago
If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:
#if FEATURE1
#endif
#if FEATURE2
#if FEATURE3VER > 2
#else
#endif
#endif
How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be…[Read more]
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Hassan replied to the topic Convert std_logic_vector to record in the forum VHDL 10 months ago
One more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than…[Read more]
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Aranzazu became a registered member 10 months ago
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Chris became a registered member 10 months ago
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FATIMA became a registered member 10 months ago
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Jim Lewis replied to the topic Convert std_logic_vector to record in the forum VHDL 10 months ago
Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/
VHDL in particular is a volunteer driven standard. Hence, it is…[Read more]
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Hassan started the topic Convert std_logic_vector to record in the forum VHDL 10 months ago
Lets take an example,
constant field2_len : integer := 8;
constant field3_len : integer := 4;
constant myrecord_len : integer := 1 + field2_len + field3_len;type MyRecord is record
field1 : std_logic;
field2 : std_logic_vector(field2_len-1 downto 0);
field3 : std_logic_vector(field3_len-1 downto 0);
end record MyRecord;Now…[Read more]
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Jim Lewis replied to the topic Creating Asynchronous Clocks in the forum OSVVM 10 months, 1 week ago
2024.07 updates CreateClock. They are breaking changes – meaning the way clock starts up is different. There was alot of unneeded complexity that was part of the old CreateClock that has been minimized – while still keeping clock changing at simulation cycle 0 (aka delta cycle 0).
If you want to preview it, see the Dev branch. Nominally it…[Read more]
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Jim Lewis replied to the topic case splitting in the forum OSVVM 10 months, 1 week ago
Just a quick note, release 2024.07 will have a CreateJitterClock:
`
procedure CreateJitterClock (
signal Clk : inout std_logic ;
signal CoverID : inout CoverageIdType ;
constant Name : in string ;
constant Period : in time ;
constant DutyCycle : in real := 0.5 ;…[Read more] -
Kameron became a registered member 10 months, 1 week ago
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William became a registered member 10 months, 1 week ago
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Jim Lewis replied to the topic Mixed language simulation and synthesis support in the forum VHDL 10 months, 1 week ago
The IEEE group that works on EDA standards in general and spawns out groups like the IEEE 1076 WG is named DASC. You can find their website here: https://dasc.org/ You can certainly work through them to form such a working group.
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