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Jim Lewis replied to the topic Support for Forcing DUT Signals via OSVVM in the forum OSVVM 1 year ago
If the signals you want to drive are on an interface, then your verification component can be built so that it triggers all error conditions.
If the signals you want to drive are deep in your design, you can test that capability at the level where those signals are exposed.
Alternately if signals you want are deep in the design and you…[Read more]
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Brad Adam started the topic Support for Forcing DUT Signals via OSVVM in the forum OSVVM 1 year ago
Hey,
So I’m not seeing anything that would lead me to believe forcing signals to a defined value is possible via OSVVM but wanted to put it out there incase I’m missing some obvious switch or something.
When pushing to fully verify our code we often get to the point that only error states are not being exercised. I would like to force a signal…[Read more]
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Jim Lewis replied to the topic Found Issue with numeric_std in the forum VHDL 1 year, 1 month ago
Hi Ken,
VHDL Issues are logged here: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issuesPlease do a search before entering a bug as it may have already been found. I too have seen at least one issue – null strings are not handled according to 1076 rules.
Best Regards,
Jim -
Ken Campbell started the topic Found Issue with numeric_std in the forum VHDL 1 year, 1 month ago
Hello,
Working on DSim VHDL it has been found that there is an error in the numeric_std which was not uncovered in previous testing.please contact me at kcampbell2@altair.com with information as to where the error can be put into a bug tracking system.
Ken
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Jim Lewis started the topic Job Post: VHDL Verification Engineer in the forum OSVVM 1 year, 1 month ago
Northrop Grumman in San Diego is looking for a Senior Principal Digital Verification Engineer. Many of the groups there are using OSVVM. See:
https://ngc.wd1.myworkdayjobs.com/Northrop_Grumman_External_Site/job/United-States-California-San-Diego/Senior-Principal-Digital-Verification-Engineer_R10169704 -
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