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OSVVM can generate a lot of test reports at end of a test, I believe the EndOfTestReports exists for this purpose.

Is this feature compatible with VUnit or does it require specific OSVVM scripts and script commands to be run before those design reports can be created?

Yes. The long term plan is to add more extensive protocol violation checks it Axi4Monitor. I think a number of them are about checking that an AXI4 manager always composes a complete transaction. I am not sure the value of them if you are developing an Axi4Subordinate (formerly known as slave).

The TbAXI4.vhd contains AXI4 Manager and Subordinate along with the Test controller/sequencer called TestCtrl. It also contains clock and reset source.

There is one more thing called Axi4Monitor. I found a source file called Axi4Monitor_dummy.vhd which has an entity but empty architecture. Does this mean that the monitor module is not yet…[Read more]

Don’t despair too much at least for Xilinx I think it will be coming. They have implemented the VHDL-2019 feature called interfaces – which is a record + mode view. A mode view specifies the IO direction of each element the record. With this, they will need to support it through all of their tools, such as Platform and Block Designer. I…[Read more]

I was suspecting that the only method will be to use a wrapper that only uses standard logic signals and then the Platform Designer and Block Designer should not have any issue. Its amazing how poor the hardware domain EDA tools are.

I am not sure how Xilinx deals with this, however, for any composite port, VHDL allows you to map composites (records or arrays) element by element, below done as a formal:
`————————————————————
Manager_1 : Axi4Manager
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port map (
–…[Read more]