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“A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.”. What does this really mean that it cannot be build with AXI-Interface in VHDL? AXI interface is just bunch of signals and the design will eventually get mapped to FPGA pins and compiled to get netlist and bitstream. Why should VHDL AXI interface…[Read more]

What does your interface look like? Are there any control signals? When do you receive a result – immediately or several clocks later? What operations does it support? What is the set of values you intend to apply to your ALU to verify it?

2024.03a addresses this issue – specifically when running interactively, EndSimulation will not be called.

That makes sense. Thanks for the update!

Hi Jeremy
Currently OSVVM is doing quit -sim when a simulation ends in error. This unfortunately is necessary to close the transcript file.

A change is coming to not do this when running interactive

Jim

That indeed fixed the issue. Thank you David. Any idea why it’s not necessary to do that for earlier versions?