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Hello Hassan.
It’s one of the fundamental concepts of VHDL: Strong Typing.

A vector is a different type than its base type.

You have mentioned a specific corner case: (0 downto 0)
As you mentioned this was the result of some generics, which means at some other time this vector could also result in e.g. (6 downto 0).

Now consider that your code…[Read more]

Hey,

This is awesome news, I really appreciate the continued updates to these libraries.

Regarding clock jitter, looking into the code in ClockRstPkg.vhd I’m not sure I fully understand what is happening with the supplied coverage ID. Has there been a documentation update which details this new function?

I would expect a jitter clock to…[Read more]

Hi Jeremy
For a simulation to run fast, a general strategy is to log wave forms (SetLogSignals) and display the waves after the simulation completes (DoWaves).

If you want to run waves during the simulation, the following scripts are run (in this order) during simulate (called by simulate or by RunTest) if they exist:

– .tcl
– .tcl
-…[Read more]

Aah I see. Yes what I was doing was overkill. Thank you. The pop procedure is sufficient for what I need to do.