Activity

Lets address, 2. Identifying Transactions:

A transaction is an abstract representation of an atomic action on an interface. For a UART transmitter, it is sending one word on the interface. For an Axi4Lite interface, it is Write and Read operations on the interface.

For the simple interface we look at in our Comprehensive VHDL…[Read more]

Hi Dave,
I suspect a proper response to this may end up being a couple of blog posts in length. Lets start with a couple of references:

Comprehensive Functional Verification by Bruce Wile, John Goss, and Wolfgang Roesner covers test plans. I have not read the whole book. It is on my some day maybe list.

Peet James Snug 2000 paper on…[Read more]

The X”DEADBEUU” you are seeing is due to the masking of the lower byte.

Hi Adam,
If you are using the OSVVM Axi4Lite VC, the best way to get word addresses is to just throw away the lower address bits and do full word writes to the interface. Hence, the transaction calls would still use the addresses X”0000″, X”0004″, X”0008″, …, but since you are throwing away the lower two address bits, the memory would see it…[Read more]

Yes, writing to a memory that supports word addressing is the more accurate way of saying this. I would like to ignore WSTRB but the issue seems to be occurring at the manager side, not the subordinate side.

As in the comment above if I do the following:

write(trans_rec, x”0001?, x”DEADBEEF”); –WSTRB = 1110

The AXIBUS data line shows t…[Read more]

Hey,

So this is an atypical use case for sure.

Usually I use the Axi4Lite VC as ‘normal’ and if, for instance, I was sending 32-bit data to some addresses I would do:
write(trans_rec, x”0000″, x”DEADBEEF”);
write(trans_rec, x”0004″, x”DEADBEEF”);
write(trans_rec, x”0008″, x”DEADBEEF”);
Where the base address is increasing…[Read more]

Hi Adam,
Is your question, how do you connect AXI4 up to a memory that only supports word addressing? The memory would ignore the lower bits of address that correspond to the byte addresses and it would ignore strb totally. If there is a write data operation as signified by Valid and Ready, then all 32 bits get written into memory. There is…[Read more]

Hi Adam,
I am not sure what that means. What are you trying to do? In Axi4Lite, strb is a byte strobe that indicates the corresponding 8 bits is part of the write. The strb will be active when Valid is active. This may be multiple clock cycles if Ready is not also active.

Does the dpRAM only accept full 32 bit writes? Maybe this device…[Read more]

Just found what I think is the answer in the AXI4_VC_user_guide on table 9.3.2 which lists WSTRB as non-configurable.

So I guess my question becomes, is this still accurate and if so, is there a known way to work around this in OSVVM?

Hi Adam,
The AxiStreamTransmitter and AxiStreamReceiver both have randomization in them. There is a corresponding test case that has good examples in it, TbStream_SendGetRandom1.vhd. You can find it in OsvvmLibraries/AXI4/AxiStream/TestCases. It was just updated (meaning just before this post) to better show the different use models for…[Read more]

Thanks very much Jim, I will take a look. I am now also working on an AXI Stream tranmitter as part of the same project. I will get back to you if I see anything interesting.

Oops. It took me until now to push the files to GitHub properly.

Agreed that SetDebugMode is enough for what you are doing. SetInteractiveMode = SetDebugMode + SetLogSignals + Stop Simulation when analyze or simulate error occurs.

I use SetInteractiveMode false when running a set of simulations in CI or as a regression as I want to see results from all tests, but SetInteractiveMode when debugging.

Thank you for this detailed response – very informative.

I found the TestDone signal in my simulator (was looking for it in the wrong part of the hierarchy) and it behaves as expected. FYI I am only using SetDebugMode and did not need to use SetInteractiveMode.