Activity

Is that the Questa Intel edition or another edition?

Hi Anna,
Two thoughts on that.

First, there is no need for an expected SLVERR to be an actual test case error. The following is from p37 of the Axi4_VC_user_guide.pdf that is in the documentation repository:

By default, the expected value for BRESP and RRESP are OKAY. When testing a subordinates response to an incorrect address, a SLVERR is…[Read more]

So it seems more check for implementation issues rather than functional.(?)
I wonder how and in wich way one could alternatively simulation LVDS issues. Foussing on driever behavior?

Hi fpgaphreak,

I have two main goals with this test bench:

– Check that pixel values generated on the sensor input appear in the appropriate form on the AXI-Stream output, and completion interrupts and status registers are set correctly
– Check that the interface logic is well-behaved in the case of errors on the LVDS inputs, i.e., no FSM…[Read more]

Hi Jim,

thanks, I appreciate your detailed response. I have started implementing the VC with most parameters as model options. Originally I wanted to create a custom transaction type, but for now I am using the Stream MIT. I use the data parameter of Send() to pass the seed for pixel-data generation and generate a complete frame. This doesn’t…[Read more]