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Jim Lewis replied to the topic Custom VC for image-sensor interface in the forum OSVVM 2 years, 7 months ago
Hi Thomas,
I try to divide the concerns into what must be done for every transaction and what is stable for a long period of time. Things that are stable for a long period of time can be set with SetModelOptions.The error injection probability is a candidate for SetModelOptions.
You may wish for things like Image Width, Height, Color Depth,…[Read more]
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Thomas started the topic Custom VC for image-sensor interface in the forum OSVVM 2 years, 7 months ago
Hi,
we’re currently looking for a verification methodology to integrate into our VHDL-based FPGA flow. I’m interested in how to create stimulus for custom chip interfaces, in this case an image sensor with a proprietary serial interface with multiple LVDS lanes. The interface module translates the LVDS input into an AXI-Stream packet with video…[Read more]
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fpgaphreak became a registered member 2 years, 7 months ago
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Mike became a registered member 2 years, 7 months ago
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Dirk replied to the topic Memory leak or not ? in the forum VHDL 2 years, 7 months ago
Hi Jim,
Thank you for your elaborate (and much appreciated) reply.
It is very useful and confirms what I feared being the case: that this is in fact a memory leak…
The first solution you suggest was actually already on my mind as a working alternative (without the memory leak). But this approach has the side-effect that an additional ‘copy…[Read more] -
Alejandro became a registered member 2 years, 7 months ago
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Jim Lewis wrote a new post 2 years, 7 months ago
As I was writing the blog about the 2022.10 Multiple Verification Component example, my focus was drawn to the issue, “How do I call transactions that iterate across an array of verification components?” […]
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Oliver became a registered member 2 years, 7 months ago
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Harry became a registered member 2 years, 7 months ago
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Angela became a registered member 2 years, 7 months ago
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Jim Lewis replied to the topic Memory leak or not ? in the forum VHDL 2 years, 7 months ago
Memory leak. I do not think the simulators are able to handle this for you.
I should note general VHDL questions like this may get a response faster on StackOverflow, however, I have indeed encountered this one and know a couple of solutions.
The simplest that I have seen, but not used (so it may have flaws) is:
`vhdl
function my_function(obj…[Read more] -
Dirk started the topic Memory leak or not ? in the forum VHDL 2 years, 7 months ago
I have a question about implementation of access type objects in VHDL.
Suppose I have a not fully constrained type, for example:type t_my_type is array(natural range<>, natural range <>) of integer;
Now suppose I want to write a function that transforms an object of this type (possibly changing the array dimensions), for example:
function…
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jangus became a registered member 2 years, 7 months ago
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Cristian became a registered member 2 years, 7 months ago
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Jim Lewis replied to the topic Passing arguments to simulation run script in the forum OSVVM 2 years, 7 months ago
Hi Anna,
Sorry, some how while answering your questions on GitHub, I missed your question here.For all others, here is a summary of the resolution of Anna’s question.
With the 2022.10 update, the same actions can be accomplished with the following call to simulate. Note while the items in square brackets are optional, if you use generic…[Read more]
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Jim Lewis wrote a new post 2 years, 7 months ago
Several times now I have been asked how to use multiple OSVVM VC, like a UART, in a simulation. This should be simple, however, there are a couple of VHDL and OSVVM got-yas.
For the 2022.10 release, I prepared […]
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Simon became a registered member 2 years, 7 months ago
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Simon became a registered member 2 years, 7 months ago
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Shahzeb became a registered member 2 years, 7 months ago
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Philippe became a registered member 2 years, 7 months ago
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