Activity
-
Panagiotis became a registered member 3 years, 4 months ago
-
Ashok replied to the topic How does genbin work? in the forum OSVVM 3 years, 4 months ago
Jim, Thanks very much. Wasn’t aware of all the documents available. Going through the documents to get better understanding.
-
Jim Lewis replied to the topic How does genbin work? in the forum OSVVM 3 years, 4 months ago
First, you are using the older, protected type based API. You might want to consider using the newer, singleton based API – it is simpler and does not require the test writer to use protected types (they are hidden internal to the singleton).
If you look at the document, OsvvmLibraries/Documentation/CoveragePkg_user_guide.pdf, you will find…[Read more]
-
Mark became a registered member 3 years, 4 months ago
-
Ralf became a registered member 3 years, 4 months ago
-
ED-DEBABE became a registered member 3 years, 4 months ago
-
Dominik became a registered member 3 years, 4 months ago
-
Ashok started the topic How does genbin work? in the forum OSVVM 3 years, 4 months ago
Brand new to OSVVM. Familiar with SystemVerilog functional coverage language.
Here’s a sample code. Question follows the code.
library OSVVM;
use OSVVM.CoveragePkg.all;architecture
signal op_code : std_logic_vector(2 downto 0);
signal mode : std_logic_vector(1 downto 0);
…
shared variable cp_opcode: CovPType;
shared variable…[Read more] -
Aritz became a registered member 3 years, 5 months ago
-
Ronald became a registered member 3 years, 5 months ago
-
nancy became a registered member 3 years, 5 months ago
-
Steve became a registered member 3 years, 5 months ago
-
Gavin became a registered member 3 years, 5 months ago
-
stephane became a registered member 3 years, 5 months ago
-
Jim Lewis replied to the topic Access signals from test harness in the forum OSVVM 3 years, 5 months ago
I try to user either a Verification Component or a Monitor to provide an abstraction layer for all interactions with the DUT.
If there need to be exceptions to this, then you can use external names in TestCtrl to access items from the DUT. To make this feasible, when creating the test harness (top level netlist that connects DUT, VC, and…[Read more]
-
Renaud became a registered member 3 years, 5 months ago
-
Cols started the topic Access signals from test harness in the forum OSVVM 3 years, 5 months ago
Hello all,
I have a question regarding signal access.
Can we access signals from the test harness in the test?
The signals I want to access are dut signals. Or do we need to access it from the test control?
Basically, I just want to read the signal value of the DUT upon reset.Thank you for your help
-
Nagella changed their profile picture 3 years, 5 months ago
-
Korwin became a registered member 3 years, 5 months ago
-
Sebastian became a registered member 3 years, 5 months ago
- Load More
