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Gianico replied to the topic AxiStreamReceiver: Multiple Drivers on Transaction Record. in the forum OSVVM 3 years, 6 months ago
Hello Jim!
Thank you very much for the very informative response.
We will apply what we have learned.
Best regards,
Nico -
Jim Lewis replied to the topic AxiStreamReceiver: Multiple Drivers on Transaction Record. in the forum OSVVM 3 years, 6 months ago
Hi Gianico,
Each AxiStreamReceiver needs its own transaction record. In the OSVVM testcases, we are using a single record named StreamRxRec. You need separate ones, such as StreamRx1Rec and StreamRx2Rec.There is an example of this done with the Axi4 interface. See directory OsvvmLibraries/AXI4/Axi4/testbench_MultipleMemory. In there see the…[Read more]
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omaima became a registered member 3 years, 6 months ago
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Gianico started the topic AxiStreamReceiver: Multiple Drivers on Transaction Record. in the forum OSVVM 3 years, 6 months ago
Hello!
I would like to consult this matter.
Currently we are involved in a project where our testbench has 2 AXI4 Stream Receiver VCs. This is due to the DUT has 2 output image streams to be checked.
In the Testcase, there are 2 processes for each instance of AXI4 Stream Receiver VC. The 2 processes are running in parallel. As a result we are…[Read more]
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Jens became a registered member 3 years, 6 months ago
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Ashok replied to the topic How does genbin work? in the forum OSVVM 3 years, 6 months ago
Jim, Thanks very much. Wasn’t aware of all the documents available. Going through the documents to get better understanding.
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Jim Lewis replied to the topic How does genbin work? in the forum OSVVM 3 years, 6 months ago
First, you are using the older, protected type based API. You might want to consider using the newer, singleton based API – it is simpler and does not require the test writer to use protected types (they are hidden internal to the singleton).
If you look at the document, OsvvmLibraries/Documentation/CoveragePkg_user_guide.pdf, you will find…[Read more]
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Ashok started the topic How does genbin work? in the forum OSVVM 3 years, 6 months ago
Brand new to OSVVM. Familiar with SystemVerilog functional coverage language.
Here’s a sample code. Question follows the code.
library OSVVM;
use OSVVM.CoveragePkg.all;architecture
signal op_code : std_logic_vector(2 downto 0);
signal mode : std_logic_vector(1 downto 0);
…
shared variable cp_opcode: CovPType;
shared variable…[Read more] -
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Jim Lewis replied to the topic Access signals from test harness in the forum OSVVM 3 years, 6 months ago
I try to user either a Verification Component or a Monitor to provide an abstraction layer for all interactions with the DUT.
If there need to be exceptions to this, then you can use external names in TestCtrl to access items from the DUT. To make this feasible, when creating the test harness (top level netlist that connects DUT, VC, and…[Read more]
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