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Hi Jim,I mailed the log files to your Synthworks Mail.Kind regardsSebastian

Sure, it is easy.   Sequences imply history.   We create history explicitly just like RTL – by using clocked processes / flip-flops.   Once you have history, this is just a simple cross product of selected current values and two previous values.   WRT sampling, in OSVVM, we trigger on transaction completion using an explicit call to…

Hi Jim, Many thanks for your answer. My problem is that i have tried every which way to get things to compile and i always get errors.My scoreboard generic package is defined like this now in a seperate design unit (i.e. a VHDL file):library IEEE;use IEEE.STD_LOGIC_1164.ALL;library osvvm;–use osvvm.OsvvmContext;use OSVVM.ScoreboardGenericPkg;use…[Read more]

Hi Torsten,In the IEEE VHDL-2008, there is only numeric_std_unsigned.   There is no “signed” package.   Jim

Hi Jim,I found in the ALDEC documentation how to merge the functional coverage using the acdb edit command.Example:## Merge functional coverage from TSSPWIPacdb edit -i "$dsn/src/Unit Test/unittest.acdb" -move -merge instance /unittest/TSSPWIP/TC* /unittest/TSSPWIP/TC3RecvErrBest regards,Jorge

Thanks, I get far better results with your workaround. If we change the seed function, we could look what kind of hash functions are used for dictionary types in languages like python. I assume, they use functions which are not cryptographic secure, but have a good uniform distribution and are very fast. But you are right, with such a change, the…[Read more]