Activity
-
Stefan became a registered member 5 years, 7 months ago
-
Andrea became a registered member 5 years, 7 months ago
-
Andrea became a registered member 5 years, 7 months ago
-
Matthew became a registered member 5 years, 8 months ago
-
Elisabet became a registered member 5 years, 8 months ago
-
Steve became a registered member 5 years, 8 months ago
-
Kulbhushan became a registered member 5 years, 8 months ago
-
Ramana became a registered member 5 years, 8 months ago
-
Jean-Philippe's profile was updated 5 years, 8 months ago
-
Barry became a registered member 5 years, 8 months ago
-
Hasan became a registered member 5 years, 8 months ago
-
Jim Lewis wrote a new post 5 years, 8 months ago
I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop […]
-
Phil's profile was updated 5 years, 8 months ago
-
Hasan became a registered member 5 years, 8 months ago
-
Alexander's profile was updated 5 years, 8 months ago
-
Martin changed their profile picture 5 years, 8 months ago
-
Marco became a registered member 5 years, 8 months ago
-
Hassan became a registered member 5 years, 8 months ago
-
Osman became a registered member 5 years, 8 months ago
-
Jim Lewis replied to the topic Intelligent Coverage Random test generation in the forum OSVVM 5 years, 8 months ago
Hi Ken,
Yes and no. SV does not have this built into it or the UVM library.OTOH, Accellera created a language that layers on top of other languages (I think VHDL too), called PSS (Portable Test and Stimulus Standard). Of course, it adds another layer of $$$$$ to your simulator budget.
Best Regards,
Jim - Load More
