VHDL-2019: the Users Standard

VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing.

Language changes were use model driven and had multiple opportunities to be pruned from implementation. The process started with a discussion of feature requests. Feature requests were then voted on and ranked. High ranked features were discussed and developed into proposals. Proposals were required to provide use models to affirm their worth and validity. Proposals were then developed into language change specifications (LCS).

The entire process was driven by volunteers – and again almost all were users. Volunteerism added another level of scrutiny to the request and/or proposal. If no one was willing to write a proposal or an LCS for an item, then no matter how high the feature or proposal was ranked, it failed to be worthy of being implemented.

This revision brings us numerous important updates, such as:
• Interfaces
• Conditional Compilation
• Protected Type Enhancements
• Shared Variables on Entity Interfaces
• API for Assert and PSL information
• API for Calling Path Information
• Generic Type Enhancements
• 64 Bit Integers
• Conditional Expressions
• API to access Date, Time, File System,

Why are these important?

Interfaces allow abstract connections between designs. Ever wanted to encapsulate all signals of an interface into a single record only to be confounded by not being able to specify the direction of elements of the record? Well now you can.

Conditional compilation. Users have requested this numerous times. Finally done!

Protected type enhancements allow VHDL verification libraries, such as OSVVM, to further improve verification capabilities. VHDL can do verification? YES! As a verification library, OSVVM provides similar capabilities to SystemVerilog+UVM and in the European FPGA market OSVVM is used more than SystemVerilog+UVM.

Shared variables on entity interfaces allow verification data structures, such as the OSVVM generic scoreboard, to be passed into a verification component.

The API for VHDL Assert allows us to report the number of Assert WARNING, ERROR, and FAILURE that occur in a simulation. Similarly the API for PSL gives us error and coverage seen by PSL. Couple these together with the error reporting capability of OSVVM and we can generate a detailed pass/fail report for a simulation.

The API for calling path information allow subprograms to provide detailed trace back information on the source of an error. I don’t know about you, but I am tired of numeric_std telling me that “to_unsigned” truncated an integer when what I called was “+”. When calling path is implemented in numeric_std, rather than just knowing “+” was the problem, we will know which call to “+” caused the problem.

Generic type enhancements allow us to create better generic packages for verification and RTL usage.

64-bit integers. The community has been asking for larger integers. Moving to 64 bits is seen as a first step toward a longer term solution.
Conditional expression enhancements allow us to use conditionals like “when else” in contexts such as declarations.

The API to access Date and Time simplifies the process to create a design build register.

VHDL-2019 was requested by users, ranked by users, scrutinized by users, written by users, and balloted by the VHDL community. As such, it should be clear to the vendor (simulator and synthesis) community that the users want these features.

There are simulator vendors out there who are actively implementing VHDL-2019. If your vendor is cannot tell you definitively if and when they will support the new features you want to use on your VHDL projects, then maybe it is time to find a vendor who will.

What about Verilog and SystemVerilog? It is clear from the Wilson Verification survey that VHDL is the preferred FPGA design language. For many applications, FPGA is the future. Just like in the software world, FLASH is usually preferred over ROM.

Here I have provided a quick summary of new features and capabilities provided by VHDL-2019. In later blog posts, I will fill in the details on the ones I am most excited about.

The VHDL standards committee work is never done. Join us in writing the next revision. See: http://www.eda-twiki.org/cgi-bin/view.cgi/P1076/WebHome