Reply To: Convert std_logic_vector to record
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July 24, 2024 at 13:30
#2537
Hassan
Member
One more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than half of it.
Anyway, I shall keep https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/ in mind.