Reply To: Using WaitForTransaction/RequestTransaction in a testbench

[Francois]

Hi Jim,

I did create my own record:

type test_command_type is (AssertResetCmd, DeassertResetCmd, AssertEnableCmd, DeassertEnableCmd, RunCounterCmd, StopCounterCmd, ReadCounterCmd, DoneCmd);
    
  type CounterRecType is
  record
    rdy     : RdyType;
    ack     : AckType;
    cmd     : test_command_type;
    counter : STD_LOGIC_VECTOR(7 downto 0);
  end record CounterRecType;

However, I keep running into this error:

# -- Compiling entity counter8_tb
# -- Compiling architecture test_harness of counter8_tb
# ** Error: ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(39): Nonresolved signal 'ManagerRec' has multiple sources.
#   Drivers:
#     ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(83):Instantiation TestCtrl1
#     ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(74):Instantiation CounterCtrl
# ** Note: ../osvvm_tb_demo_lib/hdl/counter8_tb_test_harness.vhd(89): VHDL Compiler exiting

You do the same in OsvvmLibraries/DpRam/testbench/TbDpRam.vhd with signals Manager1Rec and Manager2Rec. However, your testbench does not generate the same error.

I cannot figure out what you are doing differently not to generate this error.

Regards,

Francois