I have design a VHDL fifo and I want to add a unit that checks the fifo integrity is good, kind of a scoreboard.
What is the easiest way to achieve this goal? I was thinking of creating a reference memory , after that compare it with the fifo dut. Would this work? How can I compare two arrays from different hierarchy levels?
Is there anything special about the data that flows through the FIFO – such as checksum? Otherwise, there is no reason not to use an incrementing data pattern at the input and then check the same values at the output. The only concern with an incrementing pattern is that you drop so many that the counter wraps around and has a matching value – unlikely and you can make sure it did not happen by keeping a stimulus generation count and check count and make sure they match at the end of the test.
What you need to do with the FIFO is vary the traffic enough that you try to do a read while the FIFO is empty and try to do a write while the FIFO is full – in both cases you want to see the interface stop correctly. This can be accomplished simply by randomizing bursts of traffic and blocks of delay.