Brad Adam
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Brad Adam's profile was updated 6 months, 3 weeks ago
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Brad Adam replied to the topic Scripting dual-language testbench (VHDL / Verilog) in the forum OSVVM 6 months, 3 weeks ago
Okay, this is very helpful information and from this I believe the answer to what I am trying to do is probably no.
Looking at TestStandAlone.vhd assume there is a generate statement that decides if xMiiPhy gets created or not.
phy_gen : if C_PHY_GEN_TRUE = 1 generatexMiiPhy_1 : xMiiPhy
generic map (
MII_INTERFACE =>…[Read more] -
Brad Adam replied to the topic Scripting dual-language testbench (VHDL / Verilog) in the forum OSVVM 6 months, 3 weeks ago
Hey,
glbl is a verilog file referenced by an IP from a third party vendor.
Is it possible to set a generic for a file that is analyzed before simulation? Looking at the script users guide I would think that SetExtendedAnalyzeOptions is meant to accomplish this but I could be using the command incorrectly. Is it possible to use…[Read more]
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Brad Adam started the topic Scripting dual-language testbench (VHDL / Verilog) in the forum OSVVM 6 months, 3 weeks ago
Hello,
I’m wondering if there has been any documentation made for using some script functions with a dual-language testbench. Looking through past articles I’ve found discussion of topics that come close to what I am trying to do but none of which speak to .pro (or since I’m simulating in Riviera .do) considerations.
The core of what I am…[Read more]
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Brad Adam replied to the topic Configuring the AXI-Lite WSTRB in the forum OSVVM 10 months, 2 weeks ago
I appreciate the insight, Jim. Was approaching this from the wrong angle.
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Brad Adam replied to the topic Configuring the AXI-Lite WSTRB in the forum OSVVM 10 months, 3 weeks ago
Yes, writing to a memory that supports word addressing is the more accurate way of saying this. I would like to ignore WSTRB but the issue seems to be occurring at the manager side, not the subordinate side.
As in the comment above if I do the following:
write(trans_rec, x”0001?, x”DEADBEEF”); –WSTRB = 1110
The AXIBUS data line shows t…[Read more]
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Brad Adam replied to the topic Configuring the AXI-Lite WSTRB in the forum OSVVM 10 months, 3 weeks ago
Hey,
So this is an atypical use case for sure.
Usually I use the Axi4Lite VC as ‘normal’ and if, for instance, I was sending 32-bit data to some addresses I would do:
write(trans_rec, x”0000″, x”DEADBEEF”);
write(trans_rec, x”0004″, x”DEADBEEF”);
write(trans_rec, x”0008″, x”DEADBEEF”);
Where the base address is increasing…[Read more] -
Brad Adam replied to the topic Configuring the AXI-Lite WSTRB in the forum OSVVM 10 months, 3 weeks ago
Just found what I think is the answer in the AXI4_VC_user_guide on table 9.3.2 which lists WSTRB as non-configurable.
So I guess my question becomes, is this still accurate and if so, is there a known way to work around this in OSVVM?
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Brad Adam started the topic Configuring the AXI-Lite WSTRB in the forum OSVVM 10 months, 3 weeks ago
Hello again,
I’m using the AXI Lite manager VC to interface with a DUT which will eventually take what is written via AXI Lite and write it to a dpRAM.
The issue I’ve run into is that I see no way to properly decouple the data width from the strb width for this record. In this case my data width is 32-bits which means that the manager code…[Read more]
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Brad Adam replied to the topic Simulating Backpressure with the AXIS VC in the forum OSVVM 1 year ago
Thank you for this update, I’ll check it out in future testing.
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Brad Adam started the topic Creating Asynchronous Clocks in the forum OSVVM 1 year ago
I’m looking to create a simulation that uses two asynchronous clocks, is there a way within OSVVM to add a delay before starting a clock so that it does not begin generating at time 0 in a simulation?
I’m not seeing any options for this within the CreateClock procedure, is there possibly another function that allows this behavior?
Thanks.
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Brad Adam replied to the topic Simulating Backpressure with the AXIS VC in the forum OSVVM 1 year, 1 month ago
Thank you for the detailed response, Jim.
I misunderstood the correct way to use RECEIVE_READY_BEFORE_VALID and RECEIVE_READY_DELAY_CYCLES but this makes a lot of sense.
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Brad Adam started the topic Simulating Backpressure with the AXIS VC in the forum OSVVM 1 year, 1 month ago
Hello,
I’ve been using OSVVM for several months with great success but I’ve run into a problem with simulating backpressure. At a high level my test bench looks like the following:
AXIS Transmitter –> DUT –> AXIS Receiver
I’d like to test my DUT for operation in the case that the AXIS Receiver is not ready for more data but the transmitter…[Read more]
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Brad Adam became a registered member 2 years ago