Activity – Oliver – Open Source VHDL Verification Methodology

Oliver started the topic Xilinx not supporting VHDL anymore? in the forum VHDL 1 year, 6 months ago

I wonder if / why Xilinx doesn’t support VHDL anymore:
In the Feb 16, 2023 Xilinx document 63988 – “How to run timing simulation using Vivado Simulator?” it is stated: “There is no support for VHDL timing simulation.”
And in the Feb 16, 2023 Xilinx article “Simulating AXI interfaces with the AXI Verification IP (AXI VIP)” it says that “All of the…[Read more]

Oliver replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM 1 year, 9 months ago

Hi Jim,
thanks for the link. Now that I finally got my tools working I will have a look at it soon. The OSVVM demo tests look good and run well (not when following the old user’s guide in the OSVVM Examples zip archive on this site though). Unfortunately the simulation of Xilinx PCIe-demo-design with Vivado will not run when the language is set to…[Read more]

Oliver replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM 1 year, 11 months ago

Hi Jim,

thank you for the detailed answers!

Actually I’m looking at the PCIe test framework from Xilinx. The AXI I’m planning to verify is already included in OSVVM, as I could see. For QSPI as another task I will probably need to write my own.

Best regards
Oliver

Oliver started the topic Verification with SystemVerilog or VHDL in the forum OSVVM 1 year, 11 months ago

Hello,
regarding OSVVM for verification of FPGA design I have a question.
My colleague told me, that we need to use SystemVerilog instead of VHDL for a new project. The problem he sees is that Xilinx provides the cores in Verilog and the test framework in System-VL. Only this is automatically built and provided by the demo. If we wanted to take…[Read more]

Oliver

@oliver