OSVVM: ASIC Level VHDL Verification To UK and Beyond!

April 10, 2017 in Event, OS-VVM in general

I am getting ready for the next session of Advanced Testbenches and Verification in UK and am looking forward to meeting another group of students.

Ready to improve your VHDL verification methodology?   Come join me, Jim Lewis, the OSVVM chief architect, for the class, Advanced VHDL Testbenches and Verification, and learn OSVVM step by step.

If you want to learn what is in OSVVM, you can read the manual.  However, if you want to learn OSVVM in depth, get the why’s behind the features, and be more productive sooner, then you will be best served by joining us.

Our next class dates are:

May 22-26 Bracknell, UK Enroll with FirstEDA
May 30 -June 2 and June 12-16 Web Class Enroll with SynthWorks
July 17-21 Freiburg, Germany Enroll with PLC2


OSVVM is a complete ASIC level VHDL Verification methodology that is simple and effective for ASIC or FPGA projects of any size.   This class is a 5 day investment in time.  Our goal is that after this class you will:

  • Create a structured test environment using either transaction level models (aka verification components) or procedures (aka BFMs).
  • Use procedures to initiate interface actions (such as CpuRead, CpuWrite, …)
  • Write transaction based tests that are readable by the entire community – including RTL, system, and software engineers
  • Utilize a test strategy, such as directed, algorithmic, constrained random, Intelligent CoverageTM random, or a mix of these that is appropriate and effective for a particular test
  • Use records and OSVVM resolution functions to create simple interfaces
  • Write functional coverage to track the completion of your test plan
  • Synchronize tests using OSVVM synchronization utilities
  • Simplify error reporting using OSVVM alerts and affirmations
  • Create messages for debug and test reports using OSVVM logs and affirmations
  • Use the OSVVM generic scoreboard for self-checking
  • Use the OSVVM memory package to create memory models
  • Write a test plan that maximizes reuse throughout the entire test process.
  • Accelerate the testing process
  • Save enough time (particularly if you were not previously using these techniques) to recoup the time you invested in training on each project

Don’t be stuck doing verification the time consuming, tedious way.   It is time to simplify and expedite your verification effort using OSVVM and make your testbenches both readable and fun.

This is an interactive class – we entertain verification questions and discussions both during and after class.

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