Webinar Recording: VHDL Intelligent Coverage using OSVVM
Did you miss the SynthWorks and Aldec webinar on Intelligent Coverage and Open Source VHDL Verification Methodology (OSVVM)?
Looking to learn more about OSVVM and further advance your VHDL testbench skills, attend SynthWorks’ VHDL Testbenches and Verification class. In this class, we provide a super set of the OSVVM packages that facilitate transaction level modeling (tlm), self-checking, scoreboards, memory modeling, synchronization methods, functional coverage, and randomization. Our modeling approach is accessible by both verification and RTL designers.
We have instructor-led online classes coming up on September 3-6 and September 16-20. We have a public venue class session on August 19-23 in Portland, Oregon. Class details and enrollment information are here: