OSVVM World Tour

March 19, 2014 in Event, OS-VVM in general

In conjunction with FirstEDA, I taught the first two European sessions of our OSVVM and Transaction Level Modeling (TLM) focused Advanced VHDL Testbenches and Verification class. We had attendees from many of the major European System Companies who design and verify programmable devices (FPGAs). The skill level of the delegates was impressive and made teaching one of my favorite classes just that much more fun.

Not only is VHDL dominant in Europe, but according to the 2012 Wilson Research Functional Verification Study, VHDL is the dominant FPGA design and verification language worldwide. See figures 3 and 5 of the study.

When combined with Transaction Level Modeling (TLM), OSVVM provides VHDL with an advanced verification methodology that is competitive if not superior to SystemVerilog and UVM. While OSVVM provides advanced features, such as constrained random (good), Intelligent Coverage based randomization (better), and functional coverage (essential for any randomization based methodology), verification is not just about advanced features – it is also about simplicity, readability and familiarity of the approach – not by just verification engineers, but also by RTL engineers.

Take the next step in your VHDL Verification methodology. Join us on the OSVVM world tour of our Advanced VHDL Testbenches and Verification class.

The class next dates are below. More dates will be announced shortly. Enrollment information or links are available at SynthWorks Class Schedule

  • Baltimore, Maryland April 7-11
  • UK April 28-May 2
  • Gothenburg, Sweden May 5-9
  • On-line May 12-16 and May 27-30
  • Munich Germany July 14-18
  • UK July 21-25

Leave a reply

You must be logged in to post a comment.