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This is just the VHDL signal use model when reading it after assigning it in a process. Since RTL does not allow wait for 0 ns, it is limited to testbenches.

Verilog assignments have the same sort of issue.

Hi Ajeetha,
Next time please provide a complete testable example, such as I have provided below. Try running this.

library osvvm ;
context osvvm.OsvvmContext ;
use osvvm.ScoreboardPkg_int.all ;

ControlProc :…[Read more]

That worked, thanks. Can we bukcteize this as potential race condition?

Do:
stim : process
begin
SB_int <= NewID("COUNT_SB");
wait for 0 ns; -- let SB_int to update
report ("SB_int: " & integer'image(SB_int.Id));
i_up_or_down <= '0';
push(SB_int, 2);
. . .

I guessed that and did add a 1ns delay before calling NewID – please see the stim process above. Still no luck!

Thanks

Hi Ajeetha,
Nope. That is integer’left.

Put a “wait for 0 ns” before reading the signal. That allows a simulation cycle to go by and the signal to update to the value assigned by NewID.

Jim

Thanks, aligns with my thoughts. Yes the generator already creates/uses clock/reset procedures.

Regards
Ajeetha

Depending on what becomes the pattern, it could be a concurrent procedure call (if it encapsulates the entire process), a sequential procedure call (if it only encapsulates most of the process), or as you suggested an entity (but may be more than we need).

Also note that OSVVM’s TbUtilPkg has a CreateClock and a CreateReset