Activity
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Hassan started the topic Can OSVVM Verification Component be used in VUnit based testbench? in the forum OSVVM 1 year, 4 months ago
OSVVM offers many verification components. If the user testbench is VHDL VUnit based and uses VUnit libraries for a lot of testbench features but wants to use OSVVM verification components (e.g for AXI4), is that possible? If so, what will happen to all the TCL scripts that come with the OSVVM?
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Hassan replied to the topic Xilinx not supporting VHDL anymore? in the forum VHDL 1 year, 4 months ago
“A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.”. What does this really mean that it cannot be build with AXI-Interface in VHDL? AXI interface is just bunch of signals and the design will eventually get mapped to FPGA pins and compiled to get netlist and bitstream. Why should VHDL AXI interface…[Read more]
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Hassan started the topic AXI Verification Components, OSVVM vs UVVM in the forum OSVVM 1 year, 4 months ago
The OSVVM provides the following VC for AXI: AXI4 Master/Slave, AXI4-Lite Master/Slave and AXI-Stream Source/Sink. Coincidently, UVVM also provides VC for these busses.
I have the following questions:
1. Do the OSVVM VC for these AMBA busses support all parts of the specification for these busses?
2. What is the difference between the OSVVM VC…[Read more] -
Mike became a registered member 1 year, 4 months ago
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Karl-Petter became a registered member 1 year, 4 months ago
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Jim Lewis replied to the topic Which Transactor to use Stream or Address in the forum OSVVM 1 year, 4 months ago
What does your interface look like? Are there any control signals? When do you receive a result – immediately or several clocks later? What operations does it support? What is the set of values you intend to apply to your ALU to verify it?
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Narayanan started the topic Which Transactor to use Stream or Address in the forum OSVVM 1 year, 4 months ago
Hello, I have a simple ALU DUT which I using to learn OSVVM. The ALU requires 3 inputs (operation, src1, src2). If I wanted to use the Stream Model Transactor how should I use the StreamRecType.
a) Pack the 3 inputs into a std_logic_vector_max_c via DataToModel
b) Modify/Create new StreamRecType
c) Other?Regards,
Ryan -
Nikolei became a registered member 1 year, 4 months ago
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Gordon's profile was updated 1 year, 4 months ago
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Jim Lewis replied to the topic At the end of the simulation, AlertLogPkg.vhd must open. causes error message. in the forum OSVVM 1 year, 4 months ago
2024.03a addresses this issue – specifically when running interactively, EndSimulation will not be called.
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Ken became a registered member 1 year, 4 months ago
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Carsten became a registered member 1 year, 4 months ago
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Demetrios became a registered member 1 year, 4 months ago
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Cole became a registered member 1 year, 4 months ago
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Alex became a registered member 1 year, 4 months ago
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Nina became a registered member 1 year, 4 months ago
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Jeremy replied to the topic At the end of the simulation, AlertLogPkg.vhd must open. causes error message. in the forum OSVVM 1 year, 4 months ago
That makes sense. Thanks for the update!
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Jair became a registered member 1 year, 4 months ago
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Jim Lewis replied to the topic At the end of the simulation, AlertLogPkg.vhd must open. causes error message. in the forum OSVVM 1 year, 4 months ago
Hi Jeremy
Currently OSVVM is doing quit -sim when a simulation ends in error. This unfortunately is necessary to close the transcript file.A change is coming to not do this when running interactive
Jim
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Jeremy replied to the topic At the end of the simulation, AlertLogPkg.vhd must open. causes error message. in the forum OSVVM 1 year, 4 months ago
That indeed fixed the issue. Thank you David. Any idea why it’s not necessary to do that for earlier versions?
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