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Mos became a registered member 2 years, 7 months ago
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fpgaphreak replied to the topic Custom VC for image-sensor interface in the forum OSVVM 2 years, 7 months ago
So it seems more check for implementation issues rather than functional.(?)
I wonder how and in wich way one could alternatively simulation LVDS issues. Foussing on driever behavior? -
Bill became a registered member 2 years, 7 months ago
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Dan changed their profile picture 2 years, 7 months ago
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Thomas replied to the topic Custom VC for image-sensor interface in the forum OSVVM 2 years, 7 months ago
Hi fpgaphreak,
I have two main goals with this test bench:
– Check that pixel values generated on the sensor input appear in the appropriate form on the AXI-Stream output, and completion interrupts and status registers are set correctly
– Check that the interface logic is well-behaved in the case of errors on the LVDS inputs, i.e., no FSM…[Read more] -
Thomas replied to the topic Custom VC for image-sensor interface in the forum OSVVM 2 years, 7 months ago
Hi Jim,
thanks, I appreciate your detailed response. I have started implementing the VC with most parameters as model options. Originally I wanted to create a custom transaction type, but for now I am using the Stream MIT. I use the data parameter of Send() to pass the seed for pixel-data generation and generate a complete frame. This doesn’t…[Read more]
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Prashanth became a registered member 2 years, 7 months ago
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Ali became a registered member 2 years, 7 months ago
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jon became a registered member 2 years, 7 months ago
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Dan became a registered member 2 years, 7 months ago
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Kostas became a registered member 2 years, 7 months ago
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Ingo became a registered member 2 years, 7 months ago
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fpgaphreak replied to the topic Questasim Version in the forum OSVVM 2 years, 7 months ago
Was there any reaction of Siemens? I wonder who is working there at Questa anyway – i suggest these are the former Mentor programmers?
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fpgaphreak replied to the topic Questa-Intel & Reports in the forum OSVVM 2 years, 7 months ago
I have the same issue here, but only newer Questa. Formerly i did not recognize this. Possibly a config issue.
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fpgaphreak replied to the topic Custom VC for image-sensor interface in the forum OSVVM 2 years, 7 months ago
My question would be what the intention is in detail: Typically sensor interfaces are simulated and tested independently from the image content. Therefore I produced a test package capeable of driving various signal schemes and bahaviour into the lvds lines which can be simulated and also synthesized into an FPGA for real investigations of eye…[Read more]
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fpgaphreak replied to the topic How to improve VHDL in the forum VHDL 2 years, 7 months ago
I still do not like the ambigious way, vectors are treated agains signals, and that there is conversion required in between a(0 downto 0) = “1” instead of using “a(0) = ‘1’). See the bram addressing regarding their write enable. This is one signal only, however one uses 0…0 instead of a signal. So VHDL could be made more tolerant for that.
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fpgaphreak's profile was updated 2 years, 7 months ago
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fpgaphreak changed their profile picture 2 years, 7 months ago
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rajagopal became a registered member 2 years, 7 months ago
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Jamie became a registered member 2 years, 7 months ago
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