Activity
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Philipp became a registered member 3 years ago
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Nikos became a registered member 3 years ago
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Denis became a registered member 3 years ago
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Bruce became a registered member 3 years ago
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Jim Lewis wrote a new post 3 years ago
Abstract
According to the 2020 Wilson Verification Survey FPGA verification engineers spend 46% of their time debugging. As a result, we need good scripting to simplify running tests and good reports to […] -
omaima replied to the topic Ordre of stimulus in the forum OSVVM 3 years ago
hello , thanks for your reply .
I have another question . I have 2 inputs the first one have 1 value and the others can take a valu from 0 to 3 .
I used the GenBin function inside the AddCross procedure.
I want to get the for combinasion between the 2 inputs to get 100% coverage
while not IsCovred (ID) loop
AddCross(ID,4, GenBin(1),…[Read more] -
Gerhard became a registered member 3 years ago
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Jim Lewis wrote a new post 3 years ago
I just posted 2022.05a release.
2022.05 added html transcripts capability to a larger set of tools. Unfortunately this capability requires a new version of TCL that is not supported by older tools, such as […]
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Nagella replied to the topic GENERATION OF RANDOM BYTES USING RANDOM PACKAGE ONLY in the forum OSVVM 3 years ago
Hi Lewis,
the above provided code with loop statement gives simulator busy message in console box.
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Jim Lewis replied to the topic Ordre of stimulus in the forum OSVVM 3 years ago
Hi Omaima,
First, I should note you are using the older version of CoveragePkg that has a protected type interface. I suggest that you upgrade to the newer version that has a singleton interface. Please see CoveragePkg_user_guide.pdf in the OsvvmLibraries/Documentation.Coverage is a data structure. Calls are done in order and items…[Read more]
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Jim Lewis replied to the topic GENERATION OF RANDOM BYTES USING RANDOM PACKAGE ONLY in the forum OSVVM 3 years ago
Hi Nagella
To debug your code start by reading your code out loud. Do at least 2 iterations of your process.What we see is that you are calling InitSeed before generating each value.
Why is this a problem? Verification uses pseudo random. Each seed always produces the same sequence of values. For verification pseudo random is required so your…[Read more]
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Andres became a registered member 3 years ago
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Nagella started the topic GENERATION OF RANDOM BYTES USING RANDOM PACKAGE ONLY in the forum OSVVM 3 years ago
HI,
I am trying to generate a random bytes to the uart transmitter module.But in the output waveform only one byte is generated throughout the simulation…below is a piece of testbench code if anything is wrong pls correct me.
note:uat_data is a input signal to the uart transmitter module.
process
variable RV:RandomPType;
variable…[Read more]-
Hi Nagella
To debug your code start by reading your code out loud. Do at least 2 iterations of your process.What we see is that you are calling InitSeed before generating each value.
Why is this a problem? Verification uses pseudo random. Each seed always produces the same sequence of values. For verification pseudo random is required so…[Read more]
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Jim Lewis replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 3 years ago
Hi Michael,
I may have specified an extra attribute during simulation. You can adjust for this by doing:
SetCoverageSimulateOptions "-acdb_cov sbm -cc_all"
But it still did not report anything, so I read more into the the Aldec Riviera-PRO reference manual:
> Riviera-PRO does not automatically recognize the finite state machines from code. The…[Read more] -
Jim Lewis replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 3 years ago
Hi Michael,
The intention is that it reports statemachine options. Maybe I am missing something in the scripts?You can set the specific options you want with SetCoverageAnalyzeOptions and SetCoverageSimulateOptions. The defaults for Riviera-PRO are as follows. I thought the “m” here is for statemachines.
`
SetCoverageAnalyzeOptions…[Read more] -
Michael replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 3 years ago
Hey Jim,
One more quick question now that the expression and branch coverage report is working.
I see that Riviera has robust FSM code coverage reporting capabilities which I hope to be able to leverage in conjunction with OSVVM. I was wondering if the SetCoverageAnalyzeEnable function allows a user to gather FSM code coverage? Currently the…[Read more]
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Michael replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 3 years ago
Hey Jim,
Thanks for the quick response. You’re suggestion worked and I am now only collecting the desired coverage information.
I am not running Riviera-PRO in batch mode, but I will be able to work with the current setup thanks to your reply.
Regards,
Michael -
Jim Lewis replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 3 years ago
Hi Michael,
First a quick answer:
DoSetCoverageSimulateEnable true
before you build OSVVM libraries as well as anything else you don’t want coverage collected for.Why:
Currently when analyze is run for Riviera-PRO by default we do:
vcom -${VhdlVersion} -dbg -relax -work ${LibraryName} {*}${OptionalCommands} ${FileName}
The
-dbg
flag…[Read more] -
Michael started the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 3 years ago
Hello,
I am trying to incorporate Aldec’s code coverage with OSVVM and I seem to be running into an issue which I suspect is due to a scripting error on my part.
This is my current .pro file which I am using to compile and simulate my project, which I call using a .do file in Riviera:
(the .do file is where I source the startup.tcl and build the…[Read more] -
Jim Lewis wrote a new post 3 years ago
Abstract
Some methodologies (or frameworks) are so complex that you need a script to create initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM […] - Load More