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Jim Lewis replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
Hi Michael,
Thanks for the long winded question – it gives me the information I need.It looks like the instance name is the same for all instances of the UART.
As a result statement that constructs the ReceiveFifo is connecting them all
together. Currently this:ReceiveFifo <= NewID("ReceiveFifo", ID, ReportMode => DISABLED) ;It is…[Read more]
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Michael started the topic Generate Statement Breaks UART RX VC in the forum OSVVM 3 years, 2 months ago
Hello All,
I have a DUT which takes in serial data, deframes it, and demux’s it out to a 21 peripheral UART’s for transmission.
I have written an OSVVM testbench for this, as an exercise in familiarizing myself with OSVVM, and I have ran into one issue. Everything else works amazingly.
In my test harness, instead of declaring 21 instances of a…[Read more]
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Martin became a registered member 3 years, 3 months ago
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Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 3 years, 3 months ago
Hi Steve,
Thanks for the update. I have plans to test with Xcelium 22.03 soon.
Looking forward to seeing the results.Best Regards,
Jim -
Steve replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 3 years, 3 months ago
Hi Jim,
Thanks again for everything you do! I am just following up regarding full OSVVM support in Xcelium. Xcelium 22.03 was just released. It includes support for VHDL-2019 conditional analysis (pleasant surprise!) along with additional support of VHDL-2008 language features/constructs. OSVVM 2022.01 is pre-packaged, but I believe it is…[Read more]
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Laurent became a registered member 3 years, 3 months ago
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Jim Lewis wrote a new post 3 years, 3 months ago
SynthWorks is continuing with our monthly instructor lead, on-line VHDL classes. With our “half day” on-line format, we do on-line classes right. Accelerate your learning pace of OSVVM. For additional cla […]
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